Disk array system with controllers that automate host side of ATA interface

• US 6,549,981 B2
• Filed: 05/09/2002
• Issued: 04/15/2003
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Summit Data Systems LLC (Acacia Research Corporation)
• Original Assignee: 3Ware Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: McDonald, James Arthur, Herz, John Peter, Altman, Mitchell Allen, Smith, III, William Edward
• Primary Examiner(s): Bragdon, Reginald G.
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US10/142,562
• Publication Number:
  US 20020174297A1
• Time in Patent Office: 341 Days
• Field of Search: 710/74, 711/114, 711/102, 711/104, 711/105, 711/111, 711/112, 714/6
• US Class Current: 711/114
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A disk array system comprises a plurality of automated controllers, each of which implements a host side of a standard ATA interface protocol within automated circuitry to control a respective disk drive. Each automated controller preferably includes a command buffer for storing disk drive commands to be executed by a respective ATA drive, and a data buffer that stores I/O data being transferred to or from the ATA disk drive. In a preferred embodiment, the automated controllers are connected by a control bus to a microcontroller that dispatches disk drive commands to the automated controllers in response to I/O requests from a host computer, and are also connected by a second bus to an automated processor. The automated processor transfers I/O data between the automated controllers/ATA disk drives and a host computer, and tracks the completion statuses of pending I/O requests.

Claims

1. A disk array system, comprising:

a plurality of controllers, each controller automating a host side of an ATA protocol, without fetching and executing sequences of macro-instructions, to control a respective disk drive of a plurality of disk drives;

a processor that processes input/output data written to and read from the disk drives; and

a bus that interconnects, and carries input/output data between, the processor and each of the plurality of controllers.

2. The disk array system as in claim 1, wherein the bus is a packet-switched bus that transfers input/output data to and from the controllers in packets.

3. The disk array system as in claim 1, wherein the bus implements a round robin bus arbitration protocol to grant control thereof to individual controllers of the plurality of controllers.

4. The disk array system as in claim 1, wherein the bus implements a least-recently-used bus arbitration protocol to grant control thereof to individual controllers of the plurality of controllers.

5. The disk array system as in claim 1, wherein the bus guarantees a selected minimum input/output bandwidth to each of the plurality of controllers.

6. The disk array system as in claim 1, wherein each of the plurality of controllers implements a host side of at least an ultra ATA protocol within automated circuitry.

7. The disk array system as in claim 1, wherein each controller comprises an automated transfer engine circuit that implements at least the following types of disk drive transfer operations:

a status read operation, a command write operation, and a data transfer operation.

8. The disk array system as in claim 1, wherein each controller includes a FIFO (first-in-first-out) buffer circuit that receives and stores input/output data from a respective disk drive at a first transfer rate, and transmits buffered input/output data on the bus at a second transfer rate that is greater than the first transfer rate, the FIFO buffer circuit thereby accommodating a difference in transfer rates between the disk drive and the bus.

9. The disk array system as in claim 1, further comprising a microcontroller which dispatches disk drive commands to each of the plurality of controllers over a control bus, the control bus being separate from the bus that carries the input/output data.

10. The disk array system as in claim 9, wherein the microcontroller is programmed to implement at least one RAID configuration.

11. The disk array system as in claim 1, wherein each controller comprises a respective command buffer that stores disk drive commands to be executed by a corresponding ATA disk drive such that a new disk drive command may be dispatched to the ATA disk drive substantially immediately following execution by the ATA disk drive of a current disk drive command.

12. The disk array system as in claim 1, wherein the processor includes an automated circuit that uses tokens received from the controllers to monitor completion statuses of input/output requests.

13. The disk array system as in claim 1, further comprising said plurality of disk drives.

14. An input/output (I/O) subsystem, comprising:

an ATA (AT Attachment) disk drive; and

a controller external to the ATA disk drive and connected to the ATA disk drive by a set of signal lines;

wherein the controller implements a host side of an ATA protocol within automated circuitry, without fetching and executing sequences of macro-instructions, to control the ATA disk drive over the set of signal lines.

15. The I/O subsystem as in claim 14, wherein the automated circuitry comprises a transfer engine circuit that implements at least the following types of disk drive transfer operations:

a status read operation, a command write operation, and a data transfer operation.

16. The I/O subsystem as in claim 14, wherein the controller comprises a data buffer that stores I/O data during transfers to and from the ATA disk drive.

17. The I/O subsystem as in claim 16, wherein the controller transfers data between the data buffer and a packet-switched bus to which an array of disk drives are coupled.

18. The I/O subsystem as in claim 14, wherein the controller includes a FIFO (first-in-first-out) buffer circuit that receives and stores I/O data from the ATA disk drive at a first transfer rate, and transmits buffered I/O data on a bus at a second transfer rate that is greater than the first transfer rate, the FIFO buffer circuit thereby accommodating a difference in transfer rates between the ATA disk drive and the bus.

19. The I/O subsystem as in claim 14, wherein the controller comprises a command buffer that stores disk drive commands to be executed by the ATA disk drive such that a new disk drive command may be dispatched to the ATA disk drive substantially immediately following execution by the ATA disk drive of a current disk drive command.

20. The I/O subsystem as in claim 19, wherein the controller receives the disk drive commands over a control bus which is separate from a bus over which I/O data is transferred.

21. The I/O subsystem as in claim 19, wherein the controller prefetches and buffers a new disk drive command while the ATA disk drive is processing a current disk drive command.

22. The I/O subsystem as in claim 14, wherein the controller implements at least a standard Ultra ATA protocol within the automated circuitry.

23. The I/O subsystem as in claim 14, wherein the controller is connected to, and arbitrates for control of, a bus of a disk array controller.

24. The I/O subsystem as in claim 14, wherein the controller transmits I/O data read from the ATA disk drive on an arbitrated bus in packets, wherein at least some of the packets include target system memory addresses for transferring the I/O data to a system memory.

25. The I/O subsystem as in claim 14, wherein the set of signal lines comprises a set of standard ATA signal lines.

26. The I/O subsystem as in claim 14, further comprising a microcontroller connected to the controller by a control bus, said microcontroller programmed to implement at least one RAID configuration to control an array of ATA disk drives.

27. The I/O subsystem as in claim 14, wherein the controller is embodied within a single integrated circuit device.

28. The I/O subsystem as in claim 27, wherein the integrated circuit device is an application specific integrated circuit (ASIC) device.

29. The I/O subsystem as in claim 27, wherein the integrated circuit device is an FPGA device.

30. The I/O subsystem as in claim 27, wherein the integrated circuit device comprises a second controller that controls a second ATA disk drive.