CMOS active pixel with memory for imaging sensors

• US 6,552,745 B1
• Filed: 04/08/1998
• Issued: 04/22/2003
• Est. Priority Date: 04/08/1998
• Status: Expired due to Term

• Current Assignee: Nokia Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Perner, Frederick A.
• Primary Examiner(s): MOE, AUNG SOE
• Application Number:
  US09/057,429
• Time in Patent Office: 1,840 Days
• Field of Search: 348/308, 348/302, 348/297, 348/294, 348/241, 348/243, 348/207.99, 250/208.1, 257/292, 257/291, 257/532, 341/155, 341/172, 341/144
• US Class Current: 348/308
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

An imaging apparatus and a method of capturing and storing an image in digital form within a photosensitive area of the apparatus include integrating an array of memory cells within each pixel of the photosensitive area. Preferably, the memory cells are dual port memory cells, such that write operations can be performed in a parallel manner while reading operations are performed in a serial manner. In the preferred embodiment, each array contains a sufficient number of memory cells to store two digital words representing a photo signal and a reference signal. A comparator within each pixel operating in unison with a counter and a ramp generator captures the photo signal and the reference signal in digital form. The design of the imaging apparatus allows each pixel in the photosensitive area to capture and store the signals in a parallel manner. The parallel function of the apparatus increases the electronic shutter speed, while the integrated memory array eliminates the need for an external frame buffer memory.

Claims

1. An imaging apparatus having a photosensitive area formed by a matrix of pixels in which incident light is captured, digitized, and stored, said pixels being formed on a monolithic chip, each pixel comprising:

photodetecting means located within a pixel region of said monolithic chip for generating an analog photo signal that is representative to an intensity of said incident light on said each pixel;

analog-to-digital converting means located within said pixel region and operatively connected to said photodetecting means for transforming said analog photo signal to a digital photo signal word, said digital photo signal word being indicative of incident light intensity information; and

memory connected to said analog-to-digital means to receive said digital photo signal word, said memory including at least one memory cell located within said pixel region of said monolithic chip, each said at least one memory cell being a dual port memory cell, said dual port memory cell having a write bit line connected to receive said digital photo signal and a read bit line, said write and read bit lines being isolated such that said dual port memory cell is independently accessible with respect to read and write operations.

2. The imaging apparatus of claim 1 wherein said dual port memory cell is a dynamic random access memory cell having a bit storage device between at least one write access switch and at least one read access switch.

3. The imaging apparatus of claim 1 wherein said memory includes a plurality of memory cells, with at least as many memory cells as there are bits in said digital photo signal word.

4. The imaging apparatus of claim 3 further comprising means for generating a digital reference signal word for providing noise cancellation, with the number of said memory cells corresponding to the sum of bits of said digital photo signal word and said digital reference signal word.

5. The imaging apparatus of claim 4 wherein said digital photo signal word and said digital reference signal word are at least 8-bit digital words.

6. The imaging apparatus of claim 1 further comprising a counter operatively connected to said each pixel to provide a plurality of digital count words to said each pixel to enable parallel analog-to-digital conversions.

7. The imaging apparatus of claim 6 further comprising a ramp generator operatively connected to said each pixel to provide a ramp signal to said each pixel.

8. The imaging apparatus of claim 1 wherein said photodetecting means includes a photodiode and said monolithic chip is a semiconductor chip.

9. An imaging sensor comprising:

a monolithic semiconductor substrate;

a matrix of pixels located on said monolithic semiconductor substrate, each pixel including a photodetector and an array of memory cells, said memory cells being dual port memory cells having a storage device that is isolated by said at least two switches; and

peripheral circuitry means connected to said pixels for providing control and timing signals to said pixels and for processing signals received from said pixels.

10. The imaging sensor of claim 9 wherein said each pixel contains at least sixteen said dual port memory cells.

11. The imaging sensor of claim 9 wherein said peripheral circuitry means is located on said monolithic semiconductor substrate and includes a counter for generating a digital count word, said digital count word being simultaneously provided to each said pixel in said matrix.

12. The imaging sensor of claim 11 wherein said peripheral circuitry includes a ramp generator for supplying a ramp signal to each said pixel in said matrix.

13. The imaging sensor of claim 12 wherein each said pixel includes a comparator for comparing a photo signal generated by said photodetector with said ramp signal.

14. A method of capturing, digitizing, and storing an image using an image sensor having a plurality of pixels on a monolithic structure, said method comprising steps of:

generating a photo signal in an analog format at each pixel of said plurality of pixels, said photo signal being responsive to an intensity of incident light sensed at said each pixel;

converting said photo signal into a digital photo signal word at each of said plurality of pixels;

storing said digital photo signal word in a memory array located within each of said plurality of pixels;

generating a reference signal in an analog format at each of said pixels, said reference signal being representative of a dark frame;

converting said reference signal into a digital reference signal word at each of said pixels; and

storing said digital reference signal word in said memory array located within each of said pixels, including using separate portions of said memory array to store said digital reference signal word and said digital photo signal word.

15. The method of claim 14 wherein said step of converting said photo signal is accomplished in a parallel manner with respect to all of said pixels in said image sensor.

16. The method of claim 15 wherein said step of storing said digital photo signal word is accomplished in a parallel manner with respect to all of said pixels in said image sensor.

17. The method of claim 15 further comprising a step of selectively refreshing said digital photo signal word that has been stored in each said memory array of said plurality of pixels.

18. An imaging apparatus having a photosensitive area formed by a matrix of pixels in which incident light is captured, digitized, and stored, said pixels being formed on a monolithic chip, each particular pixel comprising:

photodetecting means located within a pixel region of said particular pixel of said monolithic chip for generating an analog photo signal that is representative to an intensity of said incident light on said particular pixel;

analog-to-digital converting means located within said pixel region and operatively connected to said photodetecting means for transforming said analog photo signal to a digital photo signal word, said digital photo signal word being indicative of incident light intensity information; and

memory having a first multi-bit storage connected to said analog-to-digital means to receive and store said digital photo signal word, said memory having a second multi-bit storage connected to store a digital reference signal word that is representative of noise associated with said particular pixel, said memory being memory cells located within said pixel region of said particular pixel.

19. The imaging apparatus of claim 18 wherein said first and second multi-bit storages include an equal number (N) of memory cells, wherein N is at least eight.