Level shifter with zero threshold device for ultra-deep submicron CMOS designs

• US 6,556,061 B1
• Filed: 02/20/2001
• Issued: 04/29/2003
• Est. Priority Date: 02/20/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chung-Hui, Wang, Wen-Tai
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/784,823
• Time in Patent Office: 798 Days
• Field of Search: 327/333, 327/306, 327/437, 327/427, 326/62, 326/81, 326/68
• US Class Current: 327/333
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A new level shifting circuit, using a zero threshold voltage device, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has input connected to the input of the level shifting circuit and output forming an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first zero threshold NMOS transistor has the gate connected to a low bias voltage and the source connected to the first NMOS transistor drain. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first zero threshold NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input and the source connected to ground. A second zero threshold NMOS transistor has the gate connected to the low bias voltage, the source connected to the second NMOS transistor drain, and the drain connected to the level shifting output. A second PMOS transistor has the gate connected to the first zero threshold NMOS transistor drain, the source connected to the high supply, and the drain connected to the level shifting output.

Claims

1. A level shifting circuit comprising:

a circuit input swinging between a low supply and ground;

a circuit output swinging between a high supply and said ground;

an inverter with input connected to said circuit input and with output forming an inverted circuit input;

a first NMOS transistor with gate connected to said circuit input and with source connected to said ground;

a first zero threshold NMOS transistor with gate connected to a low bias voltage and with source connected to said first NMOS transistor drain;

a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, and with drain connected to said first zero threshold NMOS transistor drain wherein said first PMOS transistor is a high voltage transistor;

a second NMOS transistor with gate connected to said inverted circuit input and with source connected to said ground;

a second zero threshold NMOS transistor with gate connected to said low bias voltage, with source connected to said second NMOS transistor drain, and with drain connected to said circuit output; and

a second PMOS transistor with gate connected said first zero threshold NMOS transistor drain, with source connected to said high supply, and with drain connected to said circuit output wherein said first PMOS transistor is a high voltage transistor.

2. The circuit according to claim 1 wherein said inverter comprises an NMOS transistor and a PMOS transistor.

3. The circuit according to claim 2 wherein said NMOS transistor and said PMOS transistor comprise low voltage transistors.

4. The circuit according to claim 1 wherein said first PMOS transistor and said second PMOS transistor comprise high voltage transistors.

5. The circuit according to claim 1 wherein said first NMOS transistor and said second NMOS transistor comprise low voltage transistors.

6. The circuit according to claim 1 wherein said first zero threshold NMOS transistor and said second zero threshold transistor comprise high voltage transistors.

7. The circuit according to claim 1 wherein said low supply is between about 0.5 Volts and 2.5 Volts.

8. The circuit according to claim 1 wherein said high supply is between about 3.0 Volts and 10 Volts.

9. The circuit according to claim 1 wherein said low bias voltage comprises said low supply.

10. A level shifting circuit comprising:

a circuit input swinging between a low supply and ground;

a circuit output swinging between a high supply and said ground;

an inverter with input connected to said circuit input and output forming an inverted circuit input;

a first NMOS transistor with gate connected to said circuit input, with source connected to said ground, and wherein said transistor comprises a low voltage transistor;

a first zero threshold NMOS transistor with gate connected to a low bias voltage, with source connected to said first NMOS transistor drain and wherein said transistor comprises a high voltage transistor having a thick gate oxide;

a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, with drain connected to said first zero threshold NMOS transistor drain, and wherein said transistor comprises a high voltage transistor;

a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and wherein said transistor comprises a low voltage transistor;

a second zero threshold NMOS transistor with gate connected to said low bias voltage, with source connected to said second NMOS transistor drain, with drain connected to said circuit output, and wherein said transistor comprises a high voltage transistor having a thick gate oxide; and

a second PMOS transistor with gate connected to said first zero threshold NMOS transistor drain, with source connected to said high supply, with drain connected to said circuit output, and wherein said transistor comprises a high voltage transistor.

11. The circuit according to claim 10 wherein said inverter comprises an NMOS transistor and a PMOS transistor.

12. The circuit according to claim 11 wherein said NMOS transistor and said PMOS transistor comprise low voltage transistors.

13. The circuit according to claim 10 wherein said low supply is between about 0.5 Volts and 2.5 Volts.

14. The circuit according to claim 10 wherein said high supply is between about 3.0 Volts and 10 Volts.

15. The circuit according to claim 10 wherein said low bias voltage comprises said low supply.

16. A level shifting circuit comprising:

a circuit input swinging between a low supply and ground;

a circuit output swinging between a high supply and said ground;

an inverter with input connected to said circuit input and output forming an inverted circuit input;

a first NMOS transistor with gate connected to said circuit input, with source connected to said ground, and wherein said transistor comprises a low voltage transistor;

a first zero threshold NMOS transistor with gate connected to said low supply, with source connected to said first NMOS transistor drain, and wherein said transistor comprises a high voltage transistor having a thick gate oxide;

a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, with drain connected to said first zero threshold NMOS transistor drain, and wherein said transistor comprises a high voltage transistor;

a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and wherein said transistor comprises a low voltage transistor;

a second zero threshold NMOS transistor with gate connected to said low supply, with source connected to said second NMOS transistor drain, with drain connected to said circuit output, and wherein said transistor comprises a high voltage transistor having a thick gate oxide; and

a second PMOS transistor with gate connected to said first zero threshold NMOS transistor drain, with source connected to said high supply, with drain connected to said circuit output, and wherein said transistor comprises a high voltage transistor.

17. The circuit according to claim 16 wherein said inverter comprises an NMOS transistor and a PMOS transistor.

18. The circuit according to claim 17 wherein said NMOS transistor and said PMOS transistor comprise low voltage transistors.

19. The circuit according to claim 16 wherein said low supply is between about 0.5 Volts and 2.5 Volts.

20. The circuit according to claim 16 wherein said high supply is between about 3.0 Volts and 10 Volts.