Silane treatment of low dielectric constant materials in semiconductor device manufacturing

• US 6,566,283 B1
• Filed: 02/12/2002
• Issued: 05/20/2003
• Est. Priority Date: 02/15/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hopper, Dawn, Pangrle, Suzette K., Ngo, Minh Van, You, Lu
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Owens, Beth E.
• Application Number:
  US10/073,068
• Time in Patent Office: 462 Days
• Field of Search: 438/597, 438/788, 438/792
• US Class Current: 438/788
• CPC Class Codes: H01L 21/31058 of organic layers
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.

Claims

1. A method of forming a composite dielectric on a semiconductor substrate, the method comprising:

forming a dielectric layer having an exposed surface on the substrate;

treating the exposed surface of the dielectric layer with silane gas and/or a silane plasma; and

forming a cap layer directly on the treated surface of the dielectric layer.

2. The method of claim 1, further comprising forming the dielectric by spin-on-glass techniques.

3. The method of claim 1, further comprising introducing the substrate to a plasma enhanced chemical vapor deposition (PECVD) chamber having a silane source to treat the exposed surface of the dielectric layer.

4. The method of claim 3, further comprising introducing silane together with a carrier gas to the PECVD chamber as the silane source.

5. The method of claim 3, further comprising forming the cap layer by PECVD without removing the substrate from the chamber.

6. The method of claim 1, further comprising patterning a photoresist on the cap layer and etching through the cap and dielectric layers to expose side surfaces of the cap and dielectric layers.

7. The method of claim 6, further comprising subjecting the exposed side surfaces of the cap and dielectric layers to a silane plasma.

8. The method of claim 1, further comprising forming the dielectric layer from a silsesquioxane dielectric material or derivative thereof.

9. A method of treating a dielectric layer on a semiconductor substrate, the method comprising:

forming a dielectric layer on the substrate;

forming a patterned photoresist on the dielectric layer;

etching through the dielectric layer to expose side surfaces therein; and

subjecting the side surfaces of the dielectric layer to a silane plasma.

10. The method of claim 9, further comprising

removing the patterned photoresist; and

forming a conformal barrier layer on the dielectric layer including the silane plasma treated side surfaces thereof.

11. The method of claim 10, further comprising forming a conductive layer on the conformal barrier layer and within the etched dielectric layer.

12. The method of claim 11, further comprising polishing the conductive layer to the barrier layer to form a conductive trench or plug within the dielectric layer.

13. The method of claim 12, further comprising forming a cap layer over the conductive layer and barrier layer.

14. The method of claim 9, wherein the dielectric layer comprises a porous silicon oxide.

15. The method of claim 14, further comprising depositing the silicon oxide at a thickness of about 0.3 microns to about 1 micron.

16. The composite structure of claim 12.

17. The composite structure of claim 16, wherein the conductive layer comprises aluminum, copper, titanium or alloys thereof.

18. The composite structure of claim 17, wherein the substrate comprises a single crystal silicon substrate having at least one active device region formed therein or thereon.