Memory device using hot charge carrier converters
First Claim
Patent Images
1. A memory device comprising:
- a path for charge carriers;
source and drain regions disposed at either end of the path;
a node for storing charge carriers to produce a field which alters the conductivity of the path and first and second hot-carrier diodes each for converting stored charge carriers into hot charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and for preventing charge carriers entering said source and drain regions in the absence of said voltage configuration.
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Accused Products
Abstract
A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To retain charge stored on the floating gate, the tunnel oxide is relatively thick. As a result it takes a long time, of the order of 100 μs, to program and erase the cell, Injection of charge onto the floating gate is helped by hot-electron and channel inversion effects. However, no such effects help tunnelling of charge off the floating gate, Introduction of a silicon heterostructure hot-electron diode comprising an intrinsic silicon region promotes electron transport from the floating gate during erasing cycles and so reduces the erase voltage. Furthermore, the intrinsic silicon region provides an additional barrier to charge leakage, so permitting a thinner tunnel oxide to be used and thus read/write cycles become shorter.
101 Citations
42 Claims
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1. A memory device comprising:
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a path for charge carriers;
source and drain regions disposed at either end of the path;
a node for storing charge carriers to produce a field which alters the conductivity of the path and first and second hot-carrier diodes each for converting stored charge carriers into hot charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and for preventing charge carriers entering said source and drain regions in the absence of said voltage configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A memory device comprising:
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a path for charge carriers;
a node for storing charge carriers to produce a field which alters the conductivity of the path and first and second hot-carrier diodes for converting stored charge carriers into hot;
charge carriers so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and configured to prevent charge carriers from leaving said node in the absence of said voltage configuration.- View Dependent Claims (38, 40)
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37. A memory device comprising:
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a channel for charge carriers;
a node for storing charge carriers to produce a field which alters the conductivity of the channel, a tunnel barrier disposed between said node and said path, for preventing charge carriers from entering or leaving said node, the improvement comprising a hot-carrier diode for additionally preventing charge from tunnelling from said channel to said node and said tunnel barrier being sufficiently thin to allow said node to be both charged and discharged on a sub-microsecond timescale.
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39. A memory device comprising:
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a channel for charge carriers;
a node for storing charge carriers to produce a field which alters the conductivity of the channel, a tunnel barrier disposed between said node and said path for preventing charge carriers from entering or leaving said node, the improvement comprising a hot-carrier diode for additionally preventing charge from tunnelling from said channel to said node and said tunnel barrier having a thickness between 2 to 10 nm. - View Dependent Claims (41)
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42. A memory device comprising:
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a path for charge carriers;
source and drain regions disposed at either end of the path;
a node for storing charge carriers to produce a field which alters the conductivity of the path; and
first and second hot-carrier diodes each for converting stored charge carriers into hot charge carriers inside said node so as to allow said charge carriers to leave said node and enter said source or drain regions in response to a given voltage configuration and for preventing charge carriers entering said source and drain regions in the absence of said voltage configuration.
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi Europe Ltd. (Hitachi, Ltd.)
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InventorsNakazato, Kazuo
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Primary Examiner(s)HO, HOAI V
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Application NumberUS09/732,012Publication NumberTime in Patent Office907 DaysField of Search365/185.18, 365/185.28, 365/185.29, 365/185.01, 257/315, 438/257US Class Current365/185.18CPC Class CodesH01L 29/40114 the electrodes comprising a...H01L 29/42324 Gate electrodes for transis...H01L 29/7885 Hot carrier injection from ...
