Apparatus and method for geometry operations in a 3D-graphics pipeline

• US 6,577,317 B1
• Filed: 08/20/1999
• Issued: 06/10/2003
• Est. Priority Date: 08/20/1998
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Arnold, Vaughn T., Duluk, Jerome F. Jr., Nguyen, Tuan D., Dodgen, Stephen L., Go, Shun Wai, Hessel, Richard E., Benkual, Jack
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/379,144
• Time in Patent Office: 1,390 Days
• Field of Search: 345/506, 345/505, 345/501, 345/502, 345/503, 345/504, 345/418, 345/419, 345/561
• US Class Current: 345/506
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/20 Perspective computation
• CPC Class Codes: G06T 15/30 Clipping
• CPC Class Codes: G06T 15/50 Lighting effects

Abstract

An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.

Claims

1. A geometry processing device comprising:

(A) a packet controller comprising;

(1) registers receiving;

data; and

commands encoding the type and quantity of the received data; and

(2) an interface state machine, receiving the commands, comprising;

(a) logic decoding the commands to determine the number of pipeline cycles needed to execute each of the commands, each of the pipeline cycles being a specific number of clock cycles; and

(b) logic generating a signal indicating the boundary between the pipeline cycles;

(B) one or more instruction controllers connected in a first pipeline fashion, each instruction controller comprising;

(1) a register receiving one of the commands from the previous instruction controller in the first pipeline fashion, a first of the instruction controllers receiving one of the commands from the packet controller;

(2) logic decoding the received one of the commands, the decoding being specific to the particular instruction controller of the one or more instruction controllers such that the same command is decoded differently by other of the instruction controllers;

(3) a jump table generating a first address;

(4) a program counter comprising;

(a) logic for receiving the generated first address as a current address; and

(b) logic for incrementing the current address;

(5) a micro-code instruction memory receiving the current address and outputting a first plurality of control bits; and

(6) logic receiving the signal indicating the boundary between the pipeline cycles to determine when a new one of the command is to be received; and

(C) one or more datapath units connected in a second pipeline fashion, each datapath unit corresponding to one of the pipelined instruction controllers, each datapath unit comprising;

(1) one or more multiported memories receiving input data from the previous datapath unit in the second pipeline fashion, a first of the datapath units receiving the input data from the packet controller; and

(2) one or more arithmetic units receiving second control bits derived at least in part from the first control bits from the corresponding instruction controller and computing output data based on the input data.

2. The geometry processing device of claim 1, wherein the data received by the packet controller comprises vertices in three dimensions that describe lines, points, and polygons, the descriptions comprising colors, surface normals, and texture coordinates.

3. The geometry processing device of claim 2, wherein at least one of the datapath units generates a plurality of packet types, the packet types being a color vertex packet, a spatial vertex packet, a propagated mode packet, and a propagated vertex packet.

4. The geometry processing device of claim 2, wherein at least one of the datapath units generates a propagated vertex packet, the propagated vertex packet comprising data describing a vertex that was passed through all the datapath units without modification.

5. The geometry processing device of claim 2, wherein at least one of the datapath units generates a propagated mode packet, the propagated mode packet comprising mode data that was passed through all the datapath units without modification.

6. The geometry processing device of claim 1, wherein the instruction controller further comprises:

one or more programmatically loaded memories generating third control bits from the decoded one of the commands; and

field merge logic generating at least some of the second plurality of control bits by combining at least some of the first plurality of control bits and at least some of the generated third control bits.

7. The geometry processing device of claim 1, wherein the instruction controller further comprises:

logic interleaving operations from different received one of the commands so as to keep the arithmetic units in the corresponding datapath unit busy.

8. The geometry processing device of claim 1, wherein the instruction controller further comprises:

logic generating a pipeline full signal indicating the instruction controller requires an additional one of the pipeline cycles to complete the received one of the commands, thereby preventing all other of the instruction controllers from beginning a next one of the received commands.

9. A geometry processing device for a 3D graphics rendering pipeline, the pipeline receiving graphics data and generating a rendered image, the graphics data comprising vertices, the geometry processing device comprising:

arithmetic units performing transformations and lighting operations on the graphics data, generating a first output vertex comprising;

transformed (x,y,z) coordinates;

texture coordinates, and vertex colors; and

memories for storing matrices used by the arithmetic units, the matrices received from a host processor, thereby having the geometry processing device use the matrices but not calculate values in the matrices; and

logic taking some of the graphics data and passing it through the arithmetic units unchanged to generate a second output vertex of identical format to the first vertex but comprising only data fields taken directly from parts of the graphics data.

10. A processing method comprising the steps:

receiving a stream of data;

receiving a stream of commands, each of the commands indicating;

(1) an amount of contiguous data from the stream of data that corresponds to the command;

(2) the type of data in the amount of data; and

(3) the type of processing to be performed on the amount of data; and

for each of the received commands, processing the corresponding data in a sequence of processing stages, the processing stages each performing, in a programmatically fixed number of clock cycles, the steps;

receiving a next one of the commands;

decoding the received next command to determine the indicated type of processing to be done in the processing stage;

processing a next amount of data to generate output data;

taking the programmatically fixed number of clock cycles to process the corresponding data;

at the end of the programmatically fixed number of clock cycles, outputting the output data to a next processing stage in the sequence of processing stages;

at the end of the programmatically fixed number of clock cycles, outputting the received next command to the next processing stage; and

conditionally asserting a signal indicating the received next command can not be completed in the programmatically fixed number of clock cycles, the signal being broadcast to all the processing stages, the signal causing all the stages to spend an additional set of the programmatically fixed number of clock cycles on the stages, corresponding received next command.

11. The processing method of claim 10, wherein the received command programmatically causes in all of the processing stages, the step of processing a next amount of data to output the next amount of data as the output data without alteration, thereby outputting from a final one of the processing stages output data that is identical to the corresponding amount of contiguous data from the stream of data.