Method of making multi-level wiring in a semiconductor device

• US 6,579,785 B2
• Filed: 01/24/2001
• Issued: 06/17/2003
• Est. Priority Date: 01/25/2000
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuda, Tetsuo, Hirabayashi, Hideaki, Toyoda, Hiroshi, Kaneko, Hisashi
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US09/767,724
• Publication Number:
  US 20010013617A1
• Time in Patent Office: 874 Days
• Field of Search: 438/597, 438/629, 438/687, 438/648
• US Class Current: 438/597
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53242 the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

Claims

1. A method of manufacturing a semiconductor device, which comprises:

forming an intermediate layer on an insulating layer formed in advance on a semiconductor substrate;

forming a groove in the intermediate layer and the insulating layer;

forming a first barrier layer on an inner surface of the groove;

depositing a wiring layer to thereby fill the groove with the wiring layer via the first barrier layer;

performing a flattening treatment of a surface of the wiring layer to thereby form a buried structure comprising the first barrier layer and a wiring inside the groove;

removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed to a level which is lower than a surface of the insulating layer, thus forming a recessed portion;

forming a second barrier layer above a surface of the intermediate layer as well as on an inner surface of the recessed portion;

performing a flattening treatment of a surface of the second barrier layer, thereby allowing the surface of the intermediate layer to be exposed; and

removing the intermediate layer, thereby allowing the surface of the insulating layer to be exposed.

2. The method according to claim 1, wherein said step of selectively removing the intermediate layer is followed by a step of performing a chemical mechanical polishing under a condition wherein the second barrier layer is polished.

3. The method according to claim 1, wherein said intermediate layer is formed of at least one kind of film selected from the group consisting of a carbon film, a silicon nitride film and a silicon oxide film.

4. A method of manufacturing a semiconductor device, which comprises the steps of:

forming a groove in an insulating layer formed in advance on a semiconductor substrate;

forming a first barrier layer on a surface of the insulating layer as well as on an inner surface of the groove;

depositing a wiring layer on a surface of the first barrier layer to thereby fill the groove with the wiring layer;

performing a flattening treatment of a surface of the wiring layer to thereby allow the first barrier layer to be continuously left at least on the insulating layer throughout an entire surface of the semiconductor substrate, thereby filling the groove with a wiring;

removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed to a level which is lower than a surface of the insulating layer, thus forming a recessed portion;

forming a second barrier layer on the first barrier layer as well as on the wiring by means of an electro-plating method where the first barrier layer remaining on the insulating layer is employed as an electrode; and

performing a flattening treatment of surfaces of the second barrier layer and the first barrier layer until the surface of the insulating layer is exposed.

5. The method according to claim 4, wherein said wiring layer is formed by means of an electro-plating method.

6. A method of manufacturing a semiconductor device, which comprises the steps of:

forming a conductive layer on an insulating layer formed in advance on a semiconductor substrate;

forming a groove penetrating into the conductive layer and the insulating layer;

forming a first barrier layer on a surface of the conductive layer as well as on an inner surface of the groove;

depositing a wiring layer on a surface of the first barrier layer to thereby fill the groove with the wiring layer;

performing a flattening treatment of a surface of the wiring layer to thereby allow the conductive layer to be continuously left at least on the insulating layer, thereby filling the groove with a wiring;

removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed to a level which is lower than a surface of the insulating layer, thus forming a recessed portion;

forming a second barrier layer on the conductive layer as well as on the wiring by means of an electro-plating method where the conductive layer remaining on the insulating layer is employed as an electrode; and

performing a flattening treatment of surfaces of the second barrier layer and the conductive layer until the surface of the insulating layer is exposed.

7. The method according to claim 6, wherein said wiring layer is formed by means of an electro-plating method.

8. A method of manufacturing a semiconductor device, which comprises:

forming a groove in an insulating layer formed in advance on a semiconductor substrate;

forming a first barrier layer on an inner surface of the groove;

depositing a wiring layer to thereby fill the groove with the wiring layer via the first barrier layer;

performing a flattening treatment of a surface of the wiring layer to thereby form a structure comprising the first barrier layer and a wiring which are buried inside the groove;

performing a recess etching treatment of the wiring by making use of an etching solution comprising an oxidizing agent which is reactive to a main element constituting the wiring, a complex forming agent which is capable of forming a complex together with ions of the main element constituting the wiring, and a solvent for the complex, thereby permitting the surface of the wiring to be recessed to form a recessed portion, said surface of the wiring being of convex shape;

forming a second barrier layer on the wiring as well as above the insulating layer to thereby fill the recessed portion with the second barrier layer; and

performing a flattening treatment of a surface of the second barrier layer until the surface of the insulating layer is exposed, thereby leaving the second barrier layer inside the recessed portion.

9. The method according to claim 8, wherein said oxidizing agent is at least one kind of material selected from the group consisting of an aqueous solution of hydrogen peroxide, ammonium peroxosulfate and an aqueous solution of ozone.

10. The method according to claim 8, wherein said complex forming agent is at least one kind of material selected from the group consisting of amino acid, ethylene-diamine, ethylene-diamine-tetraacetic acid and aminosulfonic acid.

11. The method according to claim 10, wherein said amino acid is glycine.

12. The method according to claim 8, wherein said solvent is water.

13. The method according to claim 8, wherein said recess etching treatment is continuously performed inside a flattening device employed in the preceding step of flattening treatment.

14. The method according to claim 8, wherein said recess etching treatment is performed inside a processing chamber employed in a washing step to be performed subsequent to the preceding step of flattening treatment.

15. The method according to claim 8, wherein said angle between the surface of the wiring and the first barrier layer at a sidewall of the groove is 60°

or more.

16. A method of manufacturing a semiconductor device, which comprises:

forming a groove in an insulating layer formed in advance on a semiconductor substrate;

forming a first barrier layer on an inner surface of the groove;

depositing a wiring layer to thereby fill the groove with the wiring layer via the first barrier layer;

performing a flattening treatment of a surface of the wiring layer to thereby form a structure comprising the first barrier layer and a wiring which are buried inside the groove;

performing a recess etching treatment of the wiring, thereby permitting the surface of the wiring to be recessed to form a recessed portion, an angle between the recessed surface of the wiring and the first barrier layer at a sidewall of the groove being 60°

or more, and said surface of the wiring being of convex shape;

forming a second barrier layer on the wiring as well as above the insulating layer to thereby fill the recessed portion with the second barrier layer; and

performing a flattening treatment of a surface of the second barrier layer until the surface of the insulating layer is exposed, thereby leaving the second barrier layer inside the recessed portion.