Transistor device having an enhanced width dimension and a method of making same

• US 6,580,122 B1
• Filed: 03/20/2001
• Issued: 06/17/2003
• Est. Priority Date: 03/20/2001
• Status: Expired due to Term

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wristers, Derick J., Cheek, Jon D., Pellerin, John G.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US09/812,521
• Time in Patent Office: 819 Days
• Field of Search: 257/283, 257/330, 257/332, 257/374, 438/270, 438/259, 438/589
• US Class Current: 257/330
• CPC Class Codes: G01N 27/414 Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS

Abstract

The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.

Claims

1. A transistor, comprising:

a semiconducting substrate;

a recessed isolation structure formed in said substrate, said isolation structure defining a recess thereabove;

a gate electrode and a gate insulation layer formed above said substrate, a portion of said gate electrode and said gate insulation layer extending into said recess above said recessed isolation structure; and

a source region and a drain region formed in said substrate.

2. The transistor of claim 1, wherein said semiconducting substrate is comprised of silicon.

3. The transistor of claim 1, wherein said recessed isolation structure is comprised of at least one of silicon dioxide and silicon oxynitride.

4. The transistor of claim 1, wherein said recessed isolation structure has a surface that is positioned approximately 1000-1500 Å

below a surface of said substrate.

5. The transistor of claim 1, wherein said recessed isolation structure is formed in a trench having a width ranging from approximately 2000-3000 Å

and a depth ranging from approximately 4000-5000 Å

.

6. The transistor of claim 1, wherein said gate electrode is comprised of polysilicon.

7. The transistor of claim 1, wherein said gate insulation layer is comprised of at least one of silicon dioxide and silicon oxynitride.

8. The transistor of claim 1, wherein said gate electrode has a thickness ranging from approximately 1000-2000 Å

.

9. The transistor of claim 1, wherein said gate insulation layer has a thickness ranging from approximately 20-50 Å

.

10. The transistor of claim 1, wherein said source region and said drain region are each comprised of an extension implant region and a source/drain implant region.

11. The transistor of claim 1, wherein said gate electrode has first and second end portions that extend into said recess.

12. The transistor of claim 11, wherein said first and second end portions extending into said recess are positioned above a portion of a sidewall of an active region of said substrate defined by said recessed isolation structure.

13. A transistor, comprising:

a semiconducting substrate comprised of silicon;

a recessed isolation structure formed in said substrate, said isolation structure defining a recess thereabove;

a gate electrode comprised of polysilicon and a gate insulation layer formed above said substrate, a portion of said gate electrode and said gate insulation layer extending into said recess above said recessed isolation structure; and

a source region and a drain region formed in said substrate.

14. The transistor of claim 13, wherein said recessed isolation structure is comprised of at least one of silicon dioxide and silicon oxynitride.

15. The transistor of claim 13, wherein said recessed isolation structure has a surface that is positioned approximately 1000-1500 Å

below a surface of said substrate.

16. The transistor of claim 13, wherein said recessed isolation structure is formed in a trench having a width ranging from approximately 2000-3000 Å

and a depth ranging from approximately 4000-5000 Å

.

17. The transistor of claim 13, wherein said gate insulation layer is comprised of at least one of silicon dioxide and silicon oxynitride.

18. The transistor of claim 13, wherein said gate electrode has a thickness ranging from approximately 1000-2000 Å

.

19. The transistor of claim 13, wherein said gate insulation layer has a thickness ranging from approximately 20-50 Å

.

20. The transistor of claim 13, wherein said source region and said drain region are each comprised of an extension implant region and a source/drain implant region.

21. The transistor of claim 13, wherein said gate electrode has first and second end portions that extend into said recess in said substrate.

22. The transistor of claim 21, wherein said first and second end portions extending into said recess in said substrate are positioned above a portion of a sidewall of an active region of said substrate defined by said recessed isolation structure.

23. A transistor, comprising:

a semiconducting substrate;

a recessed isolation structure defining an active area having an upper surface and an exposed sidewall surface;

a gate insulation layer and a gate electrode positioned above a portion of said upper surface and a portion of said exposed sidewall surface of said active area; and

a source region and a drain region formed in said active area.

24. The transistor of claim 23, wherein said semiconducting substrate is comprised of silicon.

25. The transistor of claim 23, wherein said recessed isolation structure is comprised of at least one of silicon dioxide and silicon oxynitride.

26. The transistor of claim 23, wherein said recessed isolation structure has a surface that is positioned approximately 1000-1500 Å

below a surface of said substrate.

27. The transistor of claim 23, wherein said recessed isolation structure is formed in a trench having a width ranging from approximately 2000-3000 Å

and a depth ranging from approximately 4000-5000 Å

.

28. The transistor of claim 23, wherein said gate electrode is comprised of polysilicon.

29. The transistor of claim 23, wherein said gate insulation layer is comprised of at least one of silicon dioxide and silicon oxynitride.

30. The transistor of claim 23, wherein said gate electrode has a thickness ranging from approximately 1000-2000 Å

.

31. The transistor of claim 23, wherein said gate insulation layer has a thickness ranging from approximately 20-50 Å

.

32. The transistor of claim 23, wherein said source region and said drain region are each comprised of an extension implant region and a source/drain implant region.

33. The transistor of claim 23, wherein said gate electrode has first and second end portions that extend into a recess in said substrate defined by said recessed isolation structure.

34. The transistor of claim 33, wherein said first and second end portions extending into said recess in said substrate are positioned above a portion of a sidewall of an active region of said substrate defined by said recessed isolation structure.