High performance signal structure with multiple modulation formats

• US 6,587,452 B1
• Filed: 01/04/1999
• Issued: 07/01/2003
• Est. Priority Date: 01/04/1999
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.), Seiko Epson Corporation (Seiko Group)
• Original Assignee: Golden Bridge Technology Incorporated, Seiko Epson Corporation (Seiko Group)
• Inventors: Davidovici, Sorin, Kenmochi, Nobuhiko, Hama, Norio, Iida, Izumi, Kanterakis, Emmanuel
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): LOGSDON, JOSEPH B
• Application Number:
  US09/224,722
• Time in Patent Office: 1,639 Days
• Field of Search: 370/204, 370/206, 370/342, 370/465, 370/479, 370/912, 370/208, 370/209, 370/441, 370/483, 370/536, 370/542, 375/297, 375/298, 375/300, 375/302, 375/308, 375/140, 375/150, 375/151, 375/152, 375/153, 375/322, 375/345, 455/522, 455/61, 711/202, 711/221
• US Class Current: 370/342
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04W 52/34 TPC management, i.e. sharing limited amount of power among users or channels or data types, e.g. cell loading

Abstract

A mapping memory, for use with a transmitter, for mapping a first signal segment and a second signal segment of a packet so that each signal segment has the same average power level. Each signal segment is characterized by a different modulation format. The first signal segment might use BPSK, while the second signal segment might use QAM, having multiple amplitude levels.

Claims

1. A packet transmitter or communicating data, comprising:

a demultiplexer, coupled to a data input and having a plurality of outputs, for demultiplexing the data into a plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer;

chip-sequence means for outputting a plurality of chip-sequence signals, with each chip-sequence signal orthogonal to the other chip-sequence signals in said plurality of chip-sequence signals;

a plurality of product devices, coupled to the plurality of outputs of said demultiplexer, respectively, and to said chip-sequence means, for multiplying each of the sub-data-sequence signals by a respective chip-sequence signal, thereby generating a plurality of spread-spectrum channels;

a combiner, coupled to the plurality of product devices, for algebraically combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

a header device, coupled to said combiner, for concatenating a header for chip-sequence synchronization, to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal having a first signal segment and a second signal segment;

a mapping memory, having an address port coupled to said combiner, and an input port for inputting mapping characteristics of the first signal segment of the packet-spread-spectrum signal and mapping characteristics of the second signal segment of the packet-spread-spectrum signal, said mapping memory, responsive to the first signal segment present at the address port, for mapping the first signal segment at a power level, said mapping memory, responsive to the second signal segment present at the address port, for mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the packet-spread-spectrum signal; and

a transmitter subsystem, coupled to said mapping memory, for transmitting on a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel.

2. The packet transmitter as set forth in claim 1, with said chip-sequence means including a chip-sequence generator for generating the plurality of chip-sequence signals.

3. The packet transmitter as set forth in claim 1, with said chip-sequence means including a memory for storing the plurality of chip-sequence signals.

4. A packet transmitter for communicating data, comprising:

demultiplexer means, coupled to a data input and having a plurality of outputs, for demultiplexing encoded data into a plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer means;

transmitter-spread-spectrum means, coupled to the plurality of outputs of said demultiplexer means, for spread-spectrum processing each of the sub-data-sequence signals by a respective chip-sequence signal, thereby generating a plurality of spread-spectrum channels, with the respective chip-sequence signal different from each chip-sequence signal in a plurality of chip-sequence signals for spread-spectrum processing the plurality of sub-data sequence signals, respectively, and with the plurality of chip-sequence signals commonly used by the transmitter-spread- spectrum means;

combiner means, coupled to the transmitter-spread-spectrum means, for algebraically combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

header means, coupled to said combiner means, for adding a header for chip-sequence synchronization, to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal having a first signal segment and a second signal segment;

mapping means, having an address port coupled to said header means, and an input port for inputting mapping characteristics of the first signal segment of the packet-spread-spectrum signal and mapping characteristics of the second signal segment of the packet-spread-spectrum signal, said mapping means, responsive to the first signal segment present at the address port, for mapping the first signal segment at a power level, said mapping means, responsive to the second signal segment present at the address port, for mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the packet-spread-spectrum signal; and

transmitter-subsystem means, coupled to said mapping means, for transmitting at a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel.

5. The packet transmitter as set forth in claim 4, with said transmitter-spread-spectrum means including:

generating means for generating the plurality of chip-sequence signals; and

a plurality of EXCLUSIVE-OR gates coupled between said demultiplexing means, said combiner means and said generating means, for multiplying the plurality of sub-data-sequence signals by the plurality of chip-sequence signals, respectively, thereby generating the plurality of spread-spectrum channels.

6. The packet transmitter as set forth in claim 4, with said transmitter-spread-spectrum means including a memory for storing the plurality of chip-sequence signals.

7. The packet transmitter as set forth in claim 4, further including any of an encryptor and a privacy device.

8. The packet transmitter as set forth in claim 4, with said transmitter-spread-spectrum means including a plurality of product devices for multiplying each of the sub-data-sequence signals by a respective chip-sequence signal of the plurality of chip sequence signals.

9. The packet transmitter as set forth in claim 4, with said transmitter-spread-spectrum means including a plurality of matched filters, with each matched filter having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

10. The packet transmitter as set forth in claim 4, with said transmitter-spread-spectrum means including a plurality of surface-acoustic-wave devices, with each surface-acoustic-wave device having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

11. A packet transmitter for communicating data, comprising:

a demultiplexer, coupled to a transmitter-FIFO memory and having a plurality of outputs, for demultiplexing stored data into a first plurality of sub-data-sequence signals and a second plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer;

chip-sequence means for outputting a plurality of chip-sequence signals, with each chip-sequence signal orthogonal to the other chip-sequence signals in said plurality of chip-sequence signals;

a first plurality of product devices, coupled to the plurality of outputs of said demultiplexer, respectively, and to said chip-sequence means, for multiplying each of the first plurality of sub-data-sequence signals by a chip-sequence signal of the plurality of chip-sequence signals, respectively, thereby generating a first plurality of spread-spectrum channels;

a second plurality of product devices, coupled to the plurality of outputs of said demultiplexer, respectively, and to said chip-sequence means, for multiplying each of the second plurality of sub-data-sequence signals, by a chip-sequence signal of the plurality of chip-sequence signals, respectively, thereby generating a second plurality of spread-spectrum channels;

a first combiner, coupled to the first plurality of product devices, for algebraically combining the first plurality of spread-spectrum channels as a first multichannel-spread-spectrum signal;

a first header device, coupled to said first combiner, for concatenating a header for chip-sequence synchronization, to the first multichannel-spread-spectrum signal, thereby generating a first packet-spread-spectrum signal;

a second combiner, coupled to the second plurality of product devices, for algebraically combining the second plurality of spread-spectrum channels as a second multichannel-spread-spectrum signal;

a second header device, coupled to said second combiner, for concatenating a header for chip-sequence synchronization, to the second multichannel-spread-spectrum signal, thereby generating a second packet-spread-spectrum signal;

a third combiner, coupled to said first and second header devices, for combining the first and second packet-spread-spectrum signals as a QAM packet-spread-spectrum signal having a first signal segment and a second signal segment;

a mapping memory, having an address port coupled to said third combiner, and an input port for inputting mapping characteristics of the first signal segment of the QAM packet-spread-spectrum signal and mapping characteristics of the second signal segment of the QAM packet-spread-spectrum signal, said mapping memory, responsive to the first signal segment present at the address port, for mapping the first signal segment at a power level, said mapping memory, responsive to the second signal segment present at the address port, for mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the QAM packet-spread-spectrum signal; and

a transmitter subsystem, coupled to said mapping memory, for transmitting the QAM packet-spread-spectrum signal on a carrier frequency using radio waves over a communications channel.

12. The packet transmitter as set forth in claim 11, with said chip-sequence means including a chip-sequence generator for generating the plurality of chip-sequence signals.

13. The packet transmitter as set forth in claim 11, with said chip-sequence means including a memory for storing the plurality of chip-sequence signals.

14. A packet transmitter for communicating data, comprising:

demultiplexer means, coupled to transmitter-memory means and having a plurality of outputs, for demultiplexing stored data into a first plurality of sub-data-sequence signals and a second plurality of sub-data-sequence signals, with a respective sub-data-sequence signal at a respective output of said demultiplexer means;

transmitter-spread-spectrum means, coupled to the plurality of outputs of said demultiplexer means, for spread-spectrum processing each of the first plurality of sub-data-sequence signals and each of the second plurality of sub-data-sequence signals by a chip-sequence signal of a plurality of chip-sequence signals, respectively, thereby generating a first plurality of spread-spectrum channels and a second plurality of spread-spectrum channels, with the respective chip-sequence signal different from each chip-sequence signal in the plurality of chip-sequence signals for spread-spectrum processing the first plurality of sub-data sequence signals, respectively, and with the plurality of chip-sequence signals commonly used by the transmitter-spread-spectrum means;

first combiner means, coupled to said transmitter-spread-spectrum means, for algebraically combining the first plurality of spread-spectrum channels as a first multichannel-spread-spectrum signal and for algebraically combining the second plurality of spread-spectrum channels as a second multichannel-spread-spectrum signal;

header means, coupled to said combiner means, for adding a first header, for chip-sequence synchronization, to the first multichannel-spread-spectrum signal, thereby generating a first packet-spread-spectrum signal, and for adding a second header, for chip-sequence synchronization, to the second multichannel-spread-spectrum signal, thereby generating a second packet-spread-spectrum signal;

second combiner means, coupled to said header means for combining the first packet-spread-spectrum signal and the second packet-spread-spectrum signal as a quadrature amplitude modulated (QAM) packet-spread-spectrum signal having a first signal segment and a second signal segment;

mapping means, having an address port coupled to said second combiner means, and an input port for inputting mapping characteristics of the first signal segment of the QAM packet-spread-spectrum signal and mapping characteristics of the second signal segment of the QAM packet-spread-spectrum signal, said mapping means, responsive to the first signal segment present at the address port, for mapping the first signal segment at a power level, said mapping means, responsive to the second signal segment present at the address port, for mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the QAM packet-spread-spectrum signal; and

transmitter-subsystem means, coupled to said mapping means, for transmitting at a carrier frequency the QAM packet-spread-spectrum signal using radio waves over a communications channel.

15. The packet transmitter as set forth in claim 14, with said transmitter-spread-spectrum means including:

generating means for generating the plurality of chip-sequence signals;

a first plurality of EXCLUSIVE-OR gates coupled between.said demultiplexing means, said combiner means and said generating means, for multiplying the first plurality of sub-data-sequence signals by the first plurality of chip-sequence signals, respectively, thereby generating the first plurality of spread-spectrum channels; and

a second plurality of EXCLUSIVE-OR gates coupled between said demultiplexing means, said combiner means and said generating means, for multiplying the second plurality of sub-data-sequence signals by the second plurality of chip-sequence signals, respectively, thereby generating the second plurality of spread-spectrum channels.

16. The packet transmitter as set forth in claim 14, with said transmitter-spread-spectrum means including a memory for storing the plurality of chip-sequence signals.

17. The packet transmitter as set forth in claim 14, further including any of an encryptor and a privacy device.

18. The packet transmitter as set forth in claim 14, with said transmitter-spread-spectrum means including a first plurality of product devices for multiplying each of the first plurality of sub-data-sequence signals by a respective chip-sequence signal of the plurality of chip sequence signals, and a second plurality of product devices for multiplying each of the second plurality of sub-data-sequence signals by a respective chip-sequence signal of the plurality of chip-sequence signals.

19. The packet transmitter as set forth in claim 14, with said transmitter-spread-spectrum means including a first plurality of matched filters and a second plurality of matched filters, with each of the first plurality of matched filters and each of the second plurality of matched filters having an impulse response matched to a respective chip-sequence signal of the plurality of chip-sequence signals.

20. The packet transmitter as set forth in claim 14, with said transmitter-spread-spectrum means including a first plurality of surface-acoustic-wave devices and a second plurality of surface-acoustic-wave devices, with each of the first plurality of surface-acoustic-wave devices and each of the second plurality of surface-acoustic-wave devices having an impulse response matched to a chip-sequence signal of the plurality of chip-sequence signals, respectively.

21. A method for communicating data, comprising the steps of:

demultiplexing the data into a plurality of sub-data-sequence signals;

spread-spectrum processing each of the sub-data-sequence signals by a respective chip-sequence signal, thereby generating a plurality of spread-spectrum channels;

combining the plurality of spread-spectrum channels as a multichannel-spread-spectrum signal;

concatenating a header for chip-sequence synchronization, to the multichannel-spread-spectrum signal, thereby generating a packet-spread-spectrum signal having a first signal segment and a second signal segment;

mapping the first signal segment at a power level;

mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the packet-spread-spectrum signal; and

transmitting on a carrier frequency the packet-spread-spectrum signal using radio waves over a communications channel.

22. A method for communicating data, comprising the steps of:

demultiplexing stored data into a first plurality of sub-data-sequence signals and a second plurality of sub-data-sequence signals;

spread-spectrum processing each of the first plurality of sub-data-sequence signals and each of the second plurality of sub-data-sequence signals by a chip-sequence signal of a plurality of chip-sequence signals, respectively, thereby generating a first plurality of spread-spectrum channels and a second plurality of spread-spectrum channels, with a respective chip-sequence signal different from each chip-sequence signal in the plurality of chip-sequence signals for spread-spectrum processing the first plurality of sub-data sequence signals, respectively;

combining the first plurality of spread-spectrum channels as a first multichannel-spread-spectrum signal;

combining the second plurality of spread-spectrum channels as a second multichannel-spread-spectrum signal;

adding a first header, for chip-sequence synchronization, to the first multichannel-spread-spectrum signal, thereby generating a first packet-spread-spectrum signal;

adding a second header, for chip-sequence synchronization, to the second multichannel-spread-spectrum signal, thereby generating a second packet-spread-spectrum signal;

combining the first packet-spread-spectrum signal and the second packet-spread-spectrum signal as a quadrature amplitude modulated (QAM) packet-spread-spectrum signal having a first signal segment and a second signal segment;

mapping the first signal segment at a power level;

mapping the second signal segment at the power level, thereby maintaining a constant value of the power level for the second signal segment and the first signal segment of the QAM packet-spread-spectrum signal; and

transmitting at a carrier frequency the QAM packet-spread-spectrum signal using radio waves over a communications channel.