PCI bus system testing and verification apparatus and method

• US 6,587,813 B1
• Filed: 04/11/2000
• Issued: 07/01/2003
• Est. Priority Date: 04/11/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Browen, Adam, Whitt, Jeffrey K., So, David, Nuffer, Stuart, Paulsen, Erik, Grabarek, John, Hadley, Andrew, Schmitz, William
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US09/546,786
• Time in Patent Office: 1,176 Days
• Field of Search: 702/127, 702/186, 702/182, 714/726, 714/42, 714/715, 714/30, 714/28, 714/100, 714/2, 714/3, 714/699, 714/718, 714/746, 710/100, 710/110, 710/306, 710/260, 710/313, 711/100, 711/200, 711/117, 711/147, 324/537, 324/600
• US Class Current: 702/186
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection

Abstract

An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

Claims

1. A method for the automatic testing of a PCI bus system in an information handling system, comprising the steps of:

(a) selecting a PCI command to be tested;

(b) programming a PCI master to exhibit predetermined functional behavior during a PCI transaction;

(c) asserting said PCI command to initiate a PCI transaction, said transaction comprising transfer of data over said PCI bus;

(d) transferring at least a portion of said data;

(e) monitoring and recording the behavior of said PCI bus system;

(f) determining whether a PCI protocol error has occurred;

(g) if an error has occurred in step (f), logging said error and halting execution;

(h) repeating steps (c) through (g) until it is determined that an error has occurred in step (t) or until said PCI transaction is complete; and

(i) if said PCI transaction is complete;

(j) writing data from a first memory location to a second memory location;

(k) reading data from said second memory location; and

(l) comparing data from said first memory location to data from said second memory location.

2. A method according to claim 1, wherein said PCI command comprises a memory read line command.

3. A method according to claim 1, wherein said PCI command comprises a memory read multiple command.

4. A method according to claim 1, wherein said PCI command comprises an I/O read command.

5. A method according to claim 1, wherein said PCI command comprises an I/O write command.

6. A method according to claim 1, wherein said PCI command comprises a configuration read command.

7. A method according to claim 1, wherein said PCI command comprises a configuration write command.

8. A method according to claim 1, wherein said predetermined functional behavior is in violation of PCI protocol.

9. A method according to claim 1, wherein said predetermined functional behavior is not in violation of PCI protocol.

10. A method for the automatic testing of a PCI bus system in an information handling system, comprising the steps of:

(a) initializing a PCI target device, said target device programmable to exhibit predetermined functional behavior during a PCI transaction;

(b) programming said PCI target device to exhibit said predetermined functional behavior during said PCI transaction;

(c) providing a PCI master device, said PCI master device comprising configuration address space, said configuration address space programmable to configure said PCI master device;

(d) programming said configuration address space to provide a first set of PCI bus utilization properties for said PCI master device;

(e) after said PCI target device is programmed to exhibit said predetermined functional behavior, initiating said PCI transaction, said transaction comprising transfer of data over said PCI bus;

(f) transferring at least a portion of said data;

(g) monitoring and recording the behavior of said PCI bus system;

(h) determining whether a PCI protocol error has occurred;

(i) if an error has occurred in step (h), logging said error and halting execution;

(j) repeating steps (e) through (i) until it is determined that an error has occurred in step (h) or until said PCI transaction is complete; and

(k) if said PCI transaction is complete;

(l) writing data from a first memory location to a second memory location;

(m) reading data from said second memory location; and

(n) comparing data from said first memory location to data from said second memory location.

11. A method according to claim 10, wherein said PCI command comprises a memory read line command.

12. A method according to claim 10, wherein said PCI command comprises a memory read multiple command.

13. A method according to claim 10, wherein said PCI command comprises an I/O read command.

14. A method according to claim 10, wherein said PCI command comprises an I/O write command.

15. A method according to claim 10, wherein said PCI command comprises a configuration read command.

16. A method according to claim 10, wherein said PCI command comprises a configuration write command.

17. A method according to claim 10, wherein said predetermined functional behavior is in violation of PCI protocol.

18. A method according to claim 10, wherein said predetermined functional behavior is not in violation of PCI protocol.

19. In an information handling system, an apparatus for the automatic testing and verification of a PCI bus system, comprising:

(a) means for selecting a PCI command to be tested;

(b) means for programming a PCI master to exhibit predetermined functional behavior during a PCI transaction;

(c) means for asserting said PCI command to initiate a PCI transaction, said transaction comprising transfer of data over said PCI bus;

(d) means for transferring at least a portion of said data;

(e) means for monitoring and recording the behavior of said PCI bus system;

(f) means for determining whether a PCI protocol error has occurred;

(g) means for logging an error and halting execution if an error has occurred in step (f);

(h) means for repeating steps (c) through (g) until it is determined that an error has occurred in step (f) or until said PCI transaction is complete; and

(i) if said PCI transaction is complete;

(j) means for writing data from a first memory location to a second memory location;

(k) means for reading data from said second memory location; and

(l) means for comparing data from said first memory location to data from said second memory location.

20. An apparatus according to claim 19, wherein said PCI command comprises a memory read line command.

21. An apparatus according to claim 19, wherein said PCI command comprises a memory read multiple command.

22. An apparatus according to claim 19, wherein said PCI command comprises an I/O read command.

23. An apparatus according to claim 19, wherein said PCI command comprises an I/O write command.

24. An apparatus according to claim 19, wherein said PCI command comprises a configuration read command.

25. An apparatus according to claim 19, wherein said PCI command comprises a configuration write command.

26. An apparatus according to claim 19, wherein said predetermined functional behavior is in violation of PCI protocol.

27. An apparatus according to claim 19, wherein said predetermined functional behavior is not in violation of PCI protocol.

28. In an information handling system, an apparatus for the automatic testing and verification of a PCI bus system, comprising:

(a) means for initializing a PCI target device, said target device programmable to exhibit predetermined functional behavior during a PCI transaction;

(b) means for programming said PCI target device to exhibit said predetermined functional behavior during said PCI transaction;

(c) means for providing a PCI master device, said PCI master device comprising configuration address space, said configuration address space programmable to configure said PCI master device;

(d) means for programming said configuration address space to provide a first set of PCI bus utilization properties for said PCI master device;

(e) means for initiating said PCI transaction after said PCI target device is programmed to exhibit said predetermined functional behavior, said transaction comprising transfer of data over said PCI bus;

(f) means for transferring at least a portion of said data;

(g) means for monitoring and recording the behavior of said PCI bus system;

(h) means for determining whether a PCI protocol error has occurred;

(i) means for logging an error and halting execution if an error occurs in step (h);

(j) means for repeating steps (e) through (i) until it is determined that an error has occurred in step (h) or until said PCI transaction is complete; and

(k) if said PCI transaction is complete;

(l) means for writing data from a first memory location to a second memory location;

(m) means for reading data from said second memory location; and

(n) means for comparing data from said first memory location to data from said second memory location.

29. An apparatus according to claim 28, wherein said PCI command comprises a memory read line command.

30. An apparatus according to claim 28, wherein said PCI command comprises a memory read multiple command.

31. An apparatus according to claim 28, wherein said PCI command comprises an I/O read command.

32. An apparatus according to claim 28, wherein said PCI command comprises an I/O write command.

33. An apparatus according to claim 28, wherein said PCI command comprises a configuration read command.

34. An apparatus according to claim 28, wherein said PCI command comprises a configuration write command.

35. An apparatus according to claim 28, wherein said predetermined functional behavior is in violation of PCI protocol.

36. An apparatus according to claim 28, wherein said predetermined functional behavior is not in violation of PCI protocol.

37. In an information handling system, an apparatus for the automatic testing and verification of a PCI bus system, comprising:

(a) control logic for selecting a PCI command to be tested;

(b) control logic for programming a PCI master to exhibit predetermined functional behavior during a PCI transaction;

(c) control logic for asserting said PCI command to initiate a PCI transaction, said transaction comprising transfer of data over said PCI bus;

(d) control logic for transferring at least a portion of said data;

(e) control logic for monitoring and recording the behavior of said PCI bus system;

(f) control logic for determining whether a PCI protocol error has occurred;

(g) control logic for logging said error and halting execution if an error has occurred in step (f);

(h) control logic for repeating steps (c) through (g) until it is determined that an error has occurred in step (f) or until said PCI transaction is complete; and

(i) if said PCI transaction is complete;

(j) control logic for writing data from a first memory location to a second memory location;

(k) control logic for reading data from said second memory location; and

(l) control logic for comparing data from said first memory location to data from said second memory location.

38. In an information handling system, an apparatus for the automatic testing and verification of a PCI bus system, comprising:

(a) control logic for initializing a PCI target device, said target device programmable to exhibit predetermined functional behavior during a PCI transaction;

(b) control logic for programming said PCI target device to exhibit said predetermined functional behavior during said PCI transaction;

(c) control logic for providing a PCI master device, said PCI master device comprising configuration address space, said configuration address space programmable to configure said PCI master device;

(d) control logic for programming said configuration address space to provide a first set of PCI bus utilization properties for said PCI master device;

(e) control logic for initiating said PCI transaction after said PCI target device is programmed to exhibit said predetermined functional behavior, said transaction comprising transfer of data over said PCI bus;

(f) control logic for transferring at least a portion of said data;

(g) control logic for monitoring and recording the behavior of said PCI bus system;

(h) control logic for determining whether a PCI protocol error has occurred;

(i) control logic for logging an error and halting execution if an error occurs in step (h);

(j) control logic for repeating steps (e) through (i) until it is determined that an error has occurred in step (h) or until said PCI transaction is complete; and

(k) if said PCI transaction is complete;

(l) control logic for writing data from a first memory location to a second memory location;

(m) control logic for reading data from said second memory location; and

(n) control logic for comparing data from said first memory location to data from said second memory location.

39. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for testing and verification of a PCI bus system in an information handling system, said method steps comprising:

(a) selecting a PCI command to be tested;

(b) programming a PCI master to exhibit predetermined functional behavior during a PCI transaction;

(c) asserting said PCI command to initiate a PCI transaction, said transaction comprising transfer of data over said PCI bus;

(d) transferring at least a portion of said data;

(e) monitoring and recording the behavior of said PCI bus system;

(f) determining whether a PCI protocol error has occurred;

(g) if an error has occurred in step (f), logging said error and halting execution;

(h) repeating steps (c) through (g) until it is determined that an error has occurred in step (f) or until said PCI transaction is complete; and

(i) if said PCI transaction is complete;

(j) writing data from a first memory location to a second memory location;

(k) reading data from said second memory location; and

(l) comparing data from said first memory location to data from said second memory location.

40. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for testing and verification of a PCI bus system in an information handling system, said method steps comprising:

(a) initializing a PCI target device, said target device programmable to exhibit predetermined functional behavior during a PCI transaction;

(b) programming said PCI target device to exhibit said predetermined functional behavior during said PCI transaction;

(c) providing a PCI master device, said PCI master device comprising configuration address space, said configuration address space programmable to configure said PCI master device;

(d) programming said configuration address space to provide a first set of PCI bus utilization properties for said PCI master device;

(e) after said PCI target device is programmed to exhibit said predetermined functional behavior, initiating said PCI transaction, said transaction comprising transfer of data over said PCI bus;

(f) transferring at least a portion of said data;

(g) monitoring and recording the behavior of said PCI bus system;

(h) determining whether a PCI protocol error has occurred;

(i) if an error has occurred in step (h), logging said error and halting execution;

(j) repeating steps (e) through (i) until it is determined that an error has occurred in step (h) or until said PCI transaction is complete; and

(k) if said PCI transaction is complete;

(l) writing data from a first memory location to a second memory location;

(m) reading data from said second memory location; and

(n) comparing data from said first memory location to data from said second memory location.