Integrated circuit with scan test structure

• US 6,587,981 B1
• Filed: 11/29/1999
• Issued: 07/01/2003
• Est. Priority Date: 11/29/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Muradali, Fidel, Jaarsma, Neal C.
• Primary Examiner(s): DeCady, Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/450,469
• Time in Patent Office: 1,310 Days
• Field of Search: 714/724-727, 714/729, 714/733
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test

Abstract

Scan path structures are provided for integrated circuits which contain one or more cores or levels of sub-cores embedded within the cores. Circuitry is provided to permit scan testing of scan elements, such as scan wrapper cells and scan chains, in the cores and sub-cores by providing scan paths which share access to limited numbers of scan test ports of the integrated circuit under test. This solves the problem of having sufficient scan ports at the integrated circuit boundaries for the increasingly higher number of scan paths which require access to these scan ports.

Claims

1. An integrated circuit chip having a select control, comprising:

a scan-in terminal;

a scan-out terminal;

a first scan element connectable to the scan-in terminal;

a second scan element connectable to the scan-out terminal;

a core scan element having the first and second scan elements nested therein and connectable to the scan-in terminal; and

connection logic controlled by the select control, the connection logic in a first selection connecting the first scan element to the scan-output terminal, the connection logic in a second selection connecting the second scan element to the scan-in terminal, the connection logic in a core scan element selection connecting the third scan element to the first and second scan elements.

2. The integrated circuit as claimed in claim 1 wherein:

the connection logic in a third selection connects the scan-in terminal through the first and second scan elements to the scan-out terminal.

3. The integrated circuit as claimed in claim 1 wherein:

the connection logic in a third selection bypasses the first and second scan elements to directly connect the scan-in and scan-out terminals.

4. The integrated circuit as claimed in claim 1 wherein:

the scan-in terminal, the scan-out terminal, and the connection logic in the first and second selections defines respective first and second scan paths for scan testing, the first and second scan paths being balanced to take substantially equal time for scan testing.

5. The integrated circuit as claimed in claim 1 including:

a global bus connectable to the scan-in terminal;

a terminal scan element connectable to the global bus; and

mapping logic connectable to the third scan element, the mapping logic in a first selection and a second selection respectively connecting the third and second scan elements to the scan-out terminal.

6. The integrated circuit as claimed in claim 1 including:

a third scan element connectable to the scan-out terminal;

bypass logic controlled by the select control and connectable to the scan-in terminal, the bypass logic in a first selection connecting the scan-in terminal to the scan-out terminal;

scan-out logic controlled by the select control and connectable to the bypass logic, the scan-out logic in a first and second selections respectively connecting the third and second scan elements to the scan-out terminal; and

the bypass logic in a second selection connecting the scan-out logic to the scan-out terminal.

7. An integrated circuit chip having a select control, comprising:

a chip scan-in port;

a chip scan-out port;

a first sub-core having;

a first scan-in terminal connectable to the chip scan-in port;

a first scan-out terminal;

a first wrapper cell connectable to the first scan-in and scan-out terminals; and

first connection logic controlled by the select control, the first connection logic in a first selection connecting the first scan-in and scan-out terminals and in a second selection to connecting the first wrapper cell to the first scan-out terminal;

a second sub-core having;

a second scan-in terminal connectable to the first scan-out terminal;

a second scan-out terminal connectable to the chip scan-out port;

a second wrapper cell connectable to the second scan-in and scan-out terminals; and

second connection logic controlled by the select control, the second connection logic in a first selection connecting the first wrapper cell to the scan-output terminal, the connection logic in a second selection connecting the second wrapper cell to the scan-out terminal; and

a core having the first and second sub-cores nested therein and having;

a core wrapper cell connectable to the chip scan-in port; and

core connection logic controlled by the select control, the core connection logic in a core selection connecting the core wrapper cell to the first and second scan-in terminals.

8. The integrated circuit as claimed in claim 7 wherein:

the first and second connection logic in a third selection connects the scan-in port through the first and second wrapper cells to the scan-out port.

9. The integrated circuit as claimed in claim 7 wherein:

the first and second connection logic in a third selection by passes the first and second wrapper cells to directly connect the scan-in and scan-out ports.

10. The integrated circuit as claimed in claim 7 wherein:

the scan-in port, the scan-out port, and the first and second connection logic in the first and second selections define respective first and second scan paths for scan testing, the first and second scan paths being balanced to take substantially equal time for scan testing.

11. The integrated circuit as claimed in claim 7 including:

a global bus connectable to the scan-in port;

a third wrapper cell connectable to the global bus; and

mapping logic connectable to the third wrapper cell, the mapping logic in a first selection and a second selection respectively connecting the third and second wrapper cells to the scan-out port.

12. The integrated circuit as claimed in claim 7 including:

a third wrapper cell connectable to the scan-out port;

bypass logic controlled by the select control and connectable to the scan-in port, the bypass logic in a first selection connecting the scan-in port to the scan-out port;

scan-out logic controlled by select control and connectable to the bypass logic, the scan-out logic in a first and second selections respectively connecting the third and second wrapper cells to the scan-out port; and

the bypass logic in a second selection connecting the scan-out logic to the scan-out port.

13. An integrated circuit having a select control, comprising:

a host core;

a child core in the host core;

a scan-in terminal in the host care;

a host core scan element connectable to the scan-in terminal;

scan-in connection logic connectable to the scan-in terminal and the host core scan element;

a child scan element connectable to the scan-in logic;

an internal child scan element in the child core connectable to the scan-in logic; and

connection logic responsive to the select control and connectable to the child scan element and the internal child scan element.

14. The integrated circuit as claimed in claim 13 including:

a parent core containing the host core and a scan-out terminal;

a parent core scan element in the parent core; and

scan-out mapping logic responsive to the select control and connectable to the mapping logic for selectivity connecting the parent, host, and child scan elements to the scan-out terminal.

15. The integrated circuit as claimed in claim 13 including:

a nested core in the host core;

a nested scan element in the nested core;

a nested mapping logic responsive to the select control and connectable to the nested core scan element; and

the scan-out mapping logic for selectively connecting the nested core scan element to the scan-out terminal.

16. The integrated circuit as claimed in claim 13 including:

a sub-core in a child core;

a sub-core scan element in the sub-core;

a sub-core mapping logic responsive to the select control and connectable to the sub-core scan element; and

the scan-out mapping logic for selectively connecting the sub-core scan element to the scan-out terminal.

17. The integrated circuit as claimed in claim 13 including:

a nested core in the host core;

a nested scan element in the nested core;

the connection logic connectable to form two scan paths through the child and nested scan element from the scan-in terminal to the scan-out terminal taking equal time to scan.

18. The integrated circuit as claimed in claim 13 including:

bypass connections connectable to the mapping logic for bypassing the hosts and child scan elements.

19. An integrated circuit having a select control, comprising:

a chip scan-in port;

a global bus connectable to the chip scan-in port;

a scan-in multiplexer responsive to the select control and connectable to the global bus;

a chip scan chain connectable to the global bus and the scan-in multiplexer;

a parent core;

a parent wrapper cell connectable to the scan-in multiplexer;

a parent scan chain connectable to the core wrapper cell;

a child core in parent core;

a child multiplexer responsive to the select control and connectable to the global bus and to the core scan chain;

a chain wrapper cell connectable to the child multiplexer;

a child scan chain in the child core connectable to the child wrapper cell;

a nested core in the parent core;

a nested multiplexer responsive to the select control and connectable to the global bus and to between the child wrapper cell and the child scan chain;

a nested wrapper cell connectable to the nested multiplexer;

a nested scan chain in the nested core connectable to the nested wrapper cell;

child mapping logic responsive to the select control and connectable to the child and nested scan chains;

a first scan-out multiplexer responsive to the select control and connectable to the nested mapping logic and to between the nested wrapper cell and the nested scan chain; and

a second scan-out multiplexer responsive to the select control and connectable to the scan-out port, to the first scan-out multiplexer, and to between the parent wrapper cell and the parent scan chain.

20. An integrated circuit having a select control, comprising:

a chip scan-in port;

a scan-in multiplexer responsive to the select control and connectable to the scan-in port;

a chip scan chain connectable to the scan-in port and the scan-in multiplexer;

a core wrapper cell connectable to the scan-in multiplexer;

an integrated circuit core;

a core scan chain connectable to the core wrapper cell;

a child core in the integrated circuit core;

a child multiplexer responsive to the select control and connectable to the scan-in port and to the core scan chain;

a child wrapper cell connectable to the child multiplexer;

a child scan chain in the integrated circuit core connectable to the child wrapper cell;

a nested core in the integrated circuit core;

a nested multiplexer responsive to the select control and connectable between the child wrapper cell and the child scan chain and connectable to the scan-input port;

a nexter wrapper cell connectable to the nested multiplexer;

a nested scan chain in the integrated circuit core and connectable to the nested wrapper cell;

a mapping logic responsive to the select control and connectable to the child scan chain and to the nested scan chain;

a first scan-out multiplexer responsive to the select control and connectable to between the nested wrapper cell and the nested scan chain and to mapping logic; and

a second scan-out multiplexer responsive to the select control and connectable between the core wrapper cell and the core scan chain and to the first scan-out multiplexer and the scan-out port.

21. An integrated circuit chip having a select control, comprising:

a scan-in terminal;

a scan-out terminal;

a first scan element connectable to the scan-in terminal;

a second scan element connectable to the scan-out terminal;

a core scan element having the first and the second scan elements nested therein; and

connection logic controlled by the select control, the connection logic in a first selection connecting the first scan element to the scan-output terminal, the connection logic in a second selection connecting the second scan element to the scan-in terminal;

the connection logic in a core selection connecting the core scan element to the first and second scan elements.

22. An integrated circuit chip having a scan test path, comprising:

a scan-in terminal;

a core wrapper cell connected to the scan-in terminal;

a core including;

a core internal scan chain connected to the core wrapper cell,

a first sub-core wrapper cell connected to the core internal scan chain,

a second sub-core wrapper cell connected to the first sub-core wrapper cell;

a scan-out terminal connected to the second sub-core wrapper cell whereby a scan test path extends from the scan-in terminal to the core wrapper cell to the core internal scan chain to the first sub-core wrapper to the second sub-core wrapper to the scan-out terminal.

23. An integrated circuit chip having a scan test path, comprising:

a scan-in terminal;

a sub-core wrapper cell connected to the scan-in terminal;

a sub-core including;

a sub-core internal scan chain connected to the sub-core wrapper cell and to the scan-out terminal; and

a scan-out terminal connected to the internal scan chain whereby a scan test path extends from the scan-in terminal to the sub-core wrapper cell to the sub-core internal scan chain to the scan-out terminal.

24. An integrated circuit chip having a scan test path, comprising:

a scan-in terminal;

a core wrapper cell connected to the scan-in terminal; and

a scan-out terminal connected to the core wrapper cell whereby a scan test path extends from the scan-in terminal to the core wrapper cell to the scan-out terminal.

25. An integrated circuit chip having a scan test path, comprising:

a scan-in terminal;

a first core wrapper segment cell connected to the scan-in terminal;

a first core wrapper segment cell connected to the scan-in terminal in parallel with the first core wrapper segment cell;

a first core internal scan chain connected to the first core wrapper segment cell;

a second core internal scan chain connected to the second core wrapper segment cell;

a first sub-core wrapper cell connected to the first core internal scan chain;

a second sub-core wrapper cell connected to the second core internal scan chain; and

a plurality of scan-out terminals respectively connected to the first and second sub-core wrapper cells whereby two scan test paths extend from the scan-in terminal to respective first and second core wrapper segment cells to respective first and second core internal scan chains to respective first and second sub-core wrapper cells to the plurality of scan-out terminals.