Integrated circuit with scan test structure

  • US 6,587,981 B1
  • Filed: 11/29/1999
  • Issued: 07/01/2003
  • Est. Priority Date: 11/29/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. An integrated circuit chip having a select control, comprising:

  • a scan-in terminal;

    a scan-out terminal;

    a first scan element connectable to the scan-in terminal;

    a second scan element connectable to the scan-out terminal;

    a core scan element having the first and second scan elements nested therein and connectable to the scan-in terminal; and

    connection logic controlled by the select control, the connection logic in a first selection connecting the first scan element to the scan-output terminal, the connection logic in a second selection connecting the second scan element to the scan-in terminal, the connection logic in a core scan element selection connecting the third scan element to the first and second scan elements.

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