Data transfer with highly granular cacheability control between memory and a scratchpad area

• US 6,598,136 B1
• Filed: 10/22/1997
• Issued: 07/22/2003
• Est. Priority Date: 10/06/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Norrod, Forrest E., Briggs, Willard S., Wilcox, Christopher G., Falardeau, Brian D.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/950,513
• Time in Patent Office: 2,099 Days
• Field of Search: 711/129, 711/117, 711/154, 711/165, 711/138, 345/525, 345/511, 345/562, 345/537, 345/557, 710/5
• US Class Current: 711/165
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode

Abstract

A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

Claims

1. In a processing system having a cache, a method of transferring data from a first block of memory to a second block of memory partitioned out of the cache as non-cacheable scratchpad memory, comprising the steps of:

(a) executing an instruction having a source operand;

(b) transferring data from the first block of memory to the second block of memory starting at the source operand and continuing in predetermined increments up until a predetermined size without caching data from the first block of memory, and,

(c) performing protection and privilege checks on the source operand and subsequent operands defined by the predetermined increments.

2. A method as recited in claim 1 wherein the predetermined size in step (b) is further defined by a step of specifying a size operand.

3. A method as recited in claim 1 wherein the first block of memory is system memory.

4. A method as recited in claim 1 wherein the predetermined increments terminate on a cache line boundary.

5. A method as recited in claim 1 further comprising a step of expunging the first block of memory from the cache before step (b) if the first block of memory resides in the cache.

6. A processing system with selectable cacheability for transferring data from a first block of memory to a second block of memory comprising:

(a) a cache; and

,

(b) a core, responsive to executing a predetermined instruction, to transfer a block of data in predetermined increments from the first block of memory to the second block of memory partitioned out of the cache as non-cacheable scratchpad memory without caching the first block of memory and performing address calculations with protection and privilege checks on the block of data.

7. A processing system as recited in claim 6 wherein the first block of memory is system memory.

8. A processing system as recited in claim 7 wherein the system memory includes a frame buffer.

9. A processing system as recited in claim 6 wherein the predetermined increments terminate on a cache line boundary.

10. A processing system as recited in claim 6 further comprising a graphics pipeline coupled to the cache and the core.