Chip and wafer integration process using vertical connections

• US 6,599,778 B2
• Filed: 12/19/2001
• Issued: 07/29/2003
• Est. Priority Date: 12/19/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Narayan, Chandrasekhar, Pogge, H. Bernhard, Prasad, Chandrika, Yu, Roy
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Trinh, (Vikki) Hoa B.
• Application Number:
  US10/026,103
• Publication Number:
  US 20030111733A1
• Time in Patent Office: 587 Days
• Field of Search: 438/118, 438/119, 438/122, 438/612, 438/106, 438/108, 438/614, 438/628, 438/629, 438/109, 438/622
• US Class Current: 438/118
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Claims

1. A method for fabricating a semiconductor structure including a substrate having a top surface and a bottom surface, the method comprising the steps of:

forming a feature in the top surface of the substrate;

depositing metal in the feature to make a conducting path therein;

forming a layer overlying the top surface of the substrate, the layer including an electrical conductor and a first conducting pad on a top surface of the layer, the first conducting pad being electrically connected to the feature;

attaching a plate to the layer;

thinning the substrate at the bottom surface thereof, thereby exposing the bottom of the feature; and

forming a second conducting pad on the bottom surface of the substrate to make an electrical connection to the bottom of the feature, so that the first conducting pad and the second conducting pad are electrically connected through the feature.

2. A method according to claim 1, further comprising the step of fabricating a semiconductor device in a region of the substrate adjacent to the top surface of the substrate.

3. A method according to claim 1, wherein said depositing step further comprises depositing metal so as to form a void in the feature.

4. A method according to claim 2, wherein the semiconductor device is a DRAM device.

5. A method according to claim 2, wherein the semiconductor structure comprises a first chip having a vertical electrical connection therethrough which connects the first conducting pad and the second conducting pad, and further comprising the step of:

connecting a second chip to the first chip using said vertical electrical connection so that the second chip is disposed on top of the first chip, so that the first chip and the second chip are vertically integrated.

6. A method according to claim 5, wherein the first chip includes a DRAM device and the second chip includes a processor.

7. A method according to claim 6, wherein a plurality of processor chips are disposed on a DRAM chip.

8. A method according to claim 1, wherein said thinning step comprises reducing the thickness of the substrate to less than about 100 μ

m.

9. A method according to claim 1, wherein the plate is a temporary handling plate, and further comprising the step of detaching the plate.

10. A method according to claim 9, wherein the plate is transparent to ablating radiation, and said detaching step comprises ablating an interface between the layer and the plate using ablating radiation transmitted through the plate.

11. A method according to claim 5, wherein the second chip includes another vertical electrical connection and conducting pads on a top surface of said chip.

12. A method according to claim 1, wherein the plate is a semiconductor wafer, the layer overlying the top surface of the substrate is characterized as a first layer, and said step of attaching the plate comprises the steps of:

forming a second layer on the first layer;

forming a via in the second layer to expose the first conducting pad;

forming a stud on the semiconductor wafer;

aligning the stud to the via; and

contacting the semiconductor wafer to the second layer so that the stud makes electrical connection with the first conducting pad.

13. A method according to claim 12, further comprising the steps of:

fabricating a first semiconductor device in a region of the substrate adjacent to the top surface of the substrate; and

fabricating a second semiconductor device in the semiconductor wafer, prior to said attaching step.

14. A method according to claim 13, wherein the first semiconductor device is connected to the first conducting pad through the first layer, and the second semiconductor device is connected to the stud, so that a vertical electrical connection therebetween is provided.

15. A method according to claim 14, wherein a plurality of DRAM devices are fabricated in the substrate and a plurality of processors are fabricated in the semiconductor wafer.

16. A method according to claim 12, wherein the substrate and the semiconductor wafer comprise a wafer system, and the method further comprises the step of dicing the wafer system to form a plurality of chips.