Configuring digital functions in a digital configurable macro architecture

• US 6,603,330 B1
• Filed: 07/18/2001
• Issued: 08/05/2003
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Mallard IP LLC (IP Edge LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/909,109
• Time in Patent Office: 748 Days
• Field of Search: 326/37-41, 326/47, 326/101
• US Class Current: 326/37
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits. Thus, the programmable digital circuit block is dynamically configurable from one predetermined digital function to another predetermined digital function for real-time processing.

Claims

1. A programmable digital circuit block comprising:

a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;

a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;

a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data; and

a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

2. The programmable digital circuit block as recited in claim 1 further comprising:

one or more inputs for receiving input data associated with any one of said plurality of predetermined digital functions;

one or more outputs for outputting output data associated with any one of said plurality of predetermined digital functions; and

at least one clock input for receiving a clock signal.

3. The programmable digital circuit block as recited in claim 2 wherein said configuration register configures and selects said one or more inputs, said one or more outputs, and said clock input based on said configuration data.

4. The programmable digital circuit block as recited in claim 2 further comprising:

one or more cascade inputs for receiving data from one or more adjacent programmable digital circuit blocks; and

one or more cascade outputs for outputting data to said one or more adjacent programmable digital circuit blocks.

5. The programmable digital circuit block as recited in claim 4 wherein said configuration register configures and selects said one or more cascade inputs and said one or more cascade outputs based on said configuration data.

6. The programmable digital circuit block as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

7. The programmable digital circuit block as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

8. The programmable digital circuit block as recited in claim 1 wherein said predetermined digital functions are 8-bit predetermined digital functions.

9. A programmable digital device comprising:

an array of programmable digital circuit blocks, each programmable digital circuit block comprising;

a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;

a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;

a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data; and

a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

10. The programmable digital device as recited in claim 9 wherein each programmable digital circuit block further comprises:

one or more inputs for receiving input data associated with any one of said plurality of predetermined digital functions;

one or more outputs for outputting output data associated with any one of said plurality of predetermined digital functions; and

at least one clock input for receiving a clock signal.

11. The programmable digital device as recited in claim 10 wherein said configuration register configures and selects said one or more inputs, said one or more outputs, and said clock input based on said configuration data.

12. The programmable digital device as recited in claim 10 wherein each programmable digital circuit block further comprises:

one or more cascade inputs for receiving data from one or more adjacent programmable digital circuit blocks; and

one or more cascade outputs for outputting data to said one or more adjacent programmable digital circuit blocks.

13. The programmable digital device as recited in claim 12 wherein said configuration register configures and selects said one or more cascade inputs and said one or more cascade outputs based on said configuration data.

14. The programmable digital device as recited in claim 9 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

15. The programmable digital device as recited in claim 9 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

16. The programmable digital device as recited in claim 9 wherein said predetermined digital functions are 8-bit predetermined digital functions.

17. A controller apparatus comprising:

a programmable digital circuit block comprising;

a system input for inputting a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions;

a configuration register coupled to said system input for receiving and storing said configuration data and for configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said configuration register is dynamically programmable with said configuration data;

a plurality of selectable logic circuits which are dependent on said plurality of predetermined digital functions such that to minimize size of said programmable digital circuit block, wherein said configuration register configures and selects any of said selectable logic circuits to perform one of said plurality of predetermined digital functions based on said configuration data; and

a data register coupled to said selectable logic circuits for storing data to facilitate performing any one of said plurality of predetermined digital functions.

18. The controller apparatus as recited in claim 17 wherein said programmable digital circuit block further comprises:

one or more inputs for receiving input data associated with any one of said plurality of predetermined digital functions;

one or more outputs for outputting output data associated with any one of said plurality of predetermined digital functions; and

at least one clock input for receiving a clock signal.

19. The controller apparatus as recited in claim 18 wherein said configuration register configures and selects said one or more inputs, said one or more outputs, and said clock input based on said configuration data.

20. The controller apparatus as recited in claim 18 wherein said programmable digital circuit block further comprises:

one or more cascade inputs for receiving data from one or more adjacent programmable digital circuit blocks; and

one or more cascade outputs for outputting data to said one or more adjacent programmable digital circuit blocks.

21. The controller apparatus as recited in claim 20 wherein said configuration register configures and selects said one or more cascade inputs and said one or more cascade outputs based on said configuration data.

22. The controller apparatus as recited in claim 17 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

23. The controller apparatus as recited in claim 17 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

24. The controller apparatus as recited in claim 17 wherein said predetermined digital functions are 8-bit predetermined digital functions.

25. A method of programming a programmable digital circuit block, comprising the steps of:

a) loading a plurality of configuration data corresponding to any one of a plurality of predetermined digital functions into a configuration register of said programmable digital circuit block; and

b) configuring said programmable digital circuit block to perform any one of said plurality of predetermined digital functions based on said configuration data, wherein said steps a) and b) are dynamically performed, and wherein said programmable digital circuit block includes a data register for storing data to facilitate performing any one of said plurality of predetermined digital functions.

26. The method as recited in claim 25 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.

27. The method as recited in claim 25 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.

28. The method as recited in claim 25 wherein said predetermined digital functions are 8-bit predetermined digital functions.