Telecommunications system and method for supporting an incremental redundancy error handling scheme using available gross rate channels

• US 6,604,216 B1
• Filed: 02/17/2000
• Issued: 08/05/2003
• Est. Priority Date: 12/10/1999
• Status: Expired due to Term

• Current Assignee: Optis Wireless Technology, LLC (Brevet Capital)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Eriksson, Stefan, Frodigh, Magnus, Javerbring, Stefan, Furuskar, Anders
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chase, Shelly A
• Application Number:
  US09/505,792
• Time in Patent Office: 1,265 Days
• Field of Search: 714/751, 714/752, 714/786, 714/748-749, 714/18, 375/225
• US Class Current: 714/751
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0069 Puncturing patterns
• CPC Class Codes: H04L 1/1819 with retransmission of additional or different redundancy

Abstract

A wireless communications system, transmitter, receiver and method are provided that are capable of supporting incremental redundancy error handling schemes using available gross rate channels. More specifically, the transmitter includes a coding circuit for coding a digital data block and generating a mother code word, and a reordering circuit for reordering the mother code word and generating a reordered mother code word. The transmitter also includes a modulating circuit for modulating at least one subsequence each of which has a desired number of bits taken from the reordered mother code word to fill the available bandwidth of at least one available gross rate channel. The transmitter continues to forward the modulated subsequences to the receiver until the receiver successfully decodes the digital data block.

Claims

1. A transmitter for transmitting a digital data block to a receiver, said transmitter comprising:

a coding circuit for coding the digital data block and generating a mother code word;

a reordering circuit for reordering the mother code word and generating a reordered mother code word, wherein the reordered mother code word is generated based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver; and

a modulating circuit for modulating at least one subsequence and for forwarding, to the receiver, the at least one modulated subsequence, each of the at least one modulated subsequence having a desired number of bits taken from the reordered mother code word to fill the available bandwidth of at least one available gross rate channel.

2. The transmitter of claim 1, wherein said ordering vector is based on at least one puncturing pattern, each of the at least one puncturing pattern being used to reorder the mother code word.

3. The transmitter of claim 1, wherein said receiver knows the ordering vector.

4. The transmitter of claim 1, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word.

5. The transmitter of claim 1, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word and a length of the modulated subsequence.

6. The transmitter of claim 1, wherein said modulating circuit is capable of forwarding a plurality of the modulated subsequences to the receiver until an equivalent code rate is less than a predetermined threshold rate R.

7. The transmitter of claim 6, wherein said predetermined threshold rate R is one.

8. The transmitter of claim 1, wherein said modulating circuit is capable of forwarding a plurality of the modulated subsequences to the receiver even when said transmitter fails to receive an acknowledgment signal from the receiver.

9. The transmitter of claim 1, wherein said modulating circuit is capable of forwarding one of the modulated subsequences only after said transmitter receives an acknowledgment signal from the receiver.

10. The transmitter of claim 1, wherein said transmitter is a mobile terminal or is incorporated within a wireless communications system.

11. A transmitter for supporting an error handling scheme using at least one available gross rate channel, said transmitter comprising:

a coding circuit for coding a digital data block and generating a mother code word,

a reordering circuit for reordering the mother code word and generating a reordered mother code word, wherein the reordered mother code word is generated based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver; and

a modulating circuit for modulating a subsequence taken from a first sequence of bits in the reordered mother code word and for forwarding the modulated first subsequence to the receiver using the available bandwidth of a first available gross rate channel, said modulating circuit being further capable of repeating the process of modulating and forwarding other subsequences taken from the reordered mother code word until the receiver successfully decodes the digital data block.

12. The transmitter of claim 11, wherein said error handling scheme is an incremental redundancy error handling scheme.

13. The transmitter of claim 12, wherein said incremental redundancy error handling scheme is further classified as a Type II hybrid ARQ (Automatic Repeat Request) scheme or a Type III hybrid ARQ scheme.

14. The transmitter of claim 11, wherein said ordering vector is based on at least one puncturing pattern, each of the at least one puncturing pattern being used to reorder the mother code word.

15. The transmitter of claim 11, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word.

16. The transmitter of claim 11, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word and a length of the modulated subsequence.

17. The transmitter of claim 11, wherein said modulating circuit is capable of forwarding a plurality of the modulated subsequences to the receiver until an equivalent code rate is less than a predetermined threshold rate R.

18. The transmitter of claim 17, wherein said predetermined threshold rate R is one.

19. A method for supporting an incremental redundancy error handling scheme using at least one available gross rate channel, said method comprising the steps of:

coding a digital data block to generate a mother code word;

reordering the mother code word to generate a reordered mother code word, wherein the reordered mother code word is generated based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver; and

modulating at least one subsequence from the reordered mother code word and forwarding the at least one modulated subsequence to the receiver using the available bandwidth of the at least one available gross rate channel.

20. The method of claim 19, wherein said steps of modulating and forwarding further include the steps of:

modulating a first subsequence taken from a first sequence of bits in the reordered mother code word and forwarding the modulated first subsequence to the receiver in a first available gross rate channel;

modulating a second subsequence taken from a second sequence of bits in the reordered mother code word and forwarding the modulated second subsequence word to the receiver in a second available gross rate channel; and

modulating and forwarding additional subsequences taken from additional sequences of bits in the reordered mother code word until the receiver successfully decodes the digital data block.

21. The method of claim 19, wherein said ordering vector is based on a plurality of puncturing patterns.

22. The method of claim 19, wherein said steps of modulating and forwarding further include the step of forwarding a plurality of the modulated subsequences to the receiver until an equivalent code rate is less than a predetermined threshold rate R.

23. The method of claim 22, wherein said predetermined threshold rate R is one.

24. The method of claim 19, wherein said steps of modulating and forwarding further include the step of forwarding a plurality of the modulated subsequence to the receiver even when said transmitter fails to receive an acknowledgment signal from the receiver.

25. The method of claim 19, wherein said steps of modulating and forwarding further include the step of forwarding one of the modulated subsequences only after said transmitter receives an acknowledgment signal from the receiver.

26. The method of claim 19, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word.

27. The method of claim 19, wherein each modulated subsequence includes a header indicating a starting point in the reordered mother code word and a length of the modulated subsequence.

28. The method of claim 19, wherein said transmitter is a mobile terminal or is incorporated within a wireless communications system.

29. The method of claim 19, wherein said receiver is a mobile terminal or is incorporated within a wireless communications system.

30. A wireless communications system comprising:

a receiver;

a transmitter operatively coupled to said receiver, said transmitter including;

a coding circuit for coding a digital data block and generating a mother code word;

a reordering circuit for reordering the mother code word and generating a reordered mother code word, wherein the mother code word is reordered based on an ordering vector, the ordering vector defining an order in which bits forming the reordered mother code word are to be modulated and forwarded to the receiver; and

a modulating circuit for modulating a first subsequence taken from a first sequence of bits in the reordered mother code word and forwarding the modulated first subsequence to the receiver in the available bandwidth of a first available gross rate channel, said modulating circuit being further capable of modulating a second subsequence taken from a second sequence of bits in the reordered mother code word and forwarding the modulated second subsequence to the receiver in the available bandwidth of a second available gross rate channel, said modulating circuit also being capable of repeating the process of modulating and forwarding additional subsequences taken from additional sequences of bits in the reordered mother code word until the receiver successfully decodes the digital data block.

31. The wireless communications system of claim 30, wherein said transmitter is capable of forwarding a plurality of the modulated subsequences to the receiver until an equivalent code rate is less than one.

32. The wireless communications system of claim 30, wherein said transmitter is capable of forwarding a plurality of the modulated subsequences to the receiver even when said transmitter fails to receive an acknowledgment signal from the receiver.

33. The wireless communications system of claim 30, wherein said transmitter is capable of forwarding one of the modulated subsequences only after said transmitter receives an acknowledgment signal from the receiver.

34. A transmitter comprising:

a coding circuit for coding a digital data block and generating a mother code word;

a reordering circuit for reordering the mother code word according to an ordering vector based on at least one puncturing pattern and generating a reordered mother code word, wherein the ordering vector defines an order in which bits forming the reordered mother code word are to be modulated and forwarded to a receiver; and

a modulating circuit for modulating at least one subsequence from the reordered mother code word and forwarding the at least one modulated subsequence to the receiver using at least one fixed net rate channel, wherein said at least one subsequence has as many bits as needed to obtain a desired code rate in view of at least one quality of service requirement.