Contactless interconnection system

• US 6,612,852 B1
• Filed: 04/13/2000
• Issued: 09/02/2003
• Est. Priority Date: 04/13/2000
• Status: Expired due to Term

• Current Assignee: Molex Incorporated
• Original Assignee: Molex Incorporated
• Inventors: Panella, Augusto P.
• Primary Examiner(s): PATEL, TULSIDAS C
• Application Number:
  US09/548,940
• Time in Patent Office: 1,237 Days
• Field of Search: 439/71, 439/70, 439/66, 439/950, 357/68, 361/328
• US Class Current: 439/70
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: Y10S 439/95 Electrical connector adapted to transmit electricity to mating connector without physical contact, e.g. by induction, magnetism, or electrostatic field

Abstract

A contactless interconnecting system is provided between a computer chip package and a circuit board. The chip package has a substantially planar lower surface with a pattern of discrete terminal lands. The circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. A pattern of discrete circuit pads on the upper surface are aligned with the terminal lands. A plurality of discrete interposer members are disposed between the terminal lands and the circuit pads and are in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads. The interposer members are preferably of a material having a higher dielectric constant that of the material filling the gaps between interposer members.

Claims

1. A contactless interconnecting system between a computer chip package and a circuit board, comprising:

a computer chip package having a substantially planar lower surface with a pattern of discrete terminal lands;

a circuit board having a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package and including a pattern of discrete circuit pads aligned with said terminal lands; and

a plurality of individual and discrete, dielectric interposer members extending between said terminal lands and the circuit pads, the interposer members being in a pattern corresponding to and aligned with the aligned patterns of said terminal lands and circuit pads, said interposer members each having a height sufficient to define air gaps between said interposer members.

2. The contactless interconnecting system of claim 1 wherein said terminal lands are on a lower surface of a wall of the computer chip package, the terminal lands being connected by vias through the wall to leads from a silicon wafer of the package.

3. The contactless interconnecting system of claim 1 wherein said interposer members are supported by a planar carrier member disposed between the lower surface of the chip package and the upper surface of the circuit board.

4. The contactless interconnecting system of claim 3 wherein said interposer members are overmolded in the planar carrier member.

5. The contactless interconnecting system of claim 3 wherein said planar carrier member is fabricated of dielectric elastomeric material.

6. The contactless interconnecting system of claim 1 wherein said interposer members are adhered either to said terminal lands or to said circuit pads.

7. The contactless interconnecting system of claim 1 wherein said discrete interposer members are formed of a material having a higher dielectric constant than that of the material filling said gaps.

8. A contactless interconnecting system between a computer chip package and a circuit board, comprising:

a computer chip package having a substantially planar lower surface with a pattern of discrete terminal lands;

a circuit board having a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package and including a pattern of discrete circuit pads aligned with said terminal lands; and

a plurality of discrete, dielectric interposer members supported by a generally planar carrier member disposed between the lower surface of the chip package and the upper surface of the circuit board, the interposer members being in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads, and the interposer members being of a material having a higher dielectric constant than that of the planar carrier member.

9. The contactless interconnecting system of claim 8 wherein said terminal lands are on a lower surface of a wall of the computer chip package, the terminal lands being connected by vias through the wall to leads from a silicon wafer of the package.

10. The contactless interconnecting system of claim 8 wherein said interposer members are overmolded on the planar carrier member.

11. The contactless interconnecting system of claim 8 wherein said planar carrier member is fabricated of dielectric elastomeric material.

12. A contactless interconnecting system for a computer chip comprising:

a computer chip package having a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package and including a pattern of discrete circuit pads aligned with said terminal lands; and

a plurality of discrete, dielectric interposer members disposed between the terminal lands and the circuit pads, the interposer members being adhered to one of the terminal lands and the circuit pads, the interposer members having a height sufficient to define gaps therebetween, and the interposer members being of a material having a higher dielectric constant than that of the material filling the gaps.

13. The contactless interconnecting system of claim 12 wherein said terminal lands are on a lower surface of a wall of the computer chip package, the terminal lands being connected by vias through the wall to leads from a silicon wafer of the package.

14. The contactless interconnecting system of claim 12 wherein the dielectric constant of the interposer member is at least ten times greater than the dielectric constant of the material filling the gaps.