Surface preparation prior to deposition

• US 6,613,695 B2
• Filed: 08/31/2001
• Issued: 09/02/2003
• Est. Priority Date: 11/24/2000
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: Pomarede, Christophe F., Roberts, Jeff, Shero, Eric J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/944,734
• Publication Number:
  US 20020098627A1
• Time in Patent Office: 732 Days
• Field of Search: 438/767, 438/769, 438/775, 438/795, 438/974, 438/680, 438/840, 438/785, 438/786, 438/792
• US Class Current: 438/767
• CPC Class Codes: C23C 16/0218 in a reactive atmosphere C23C16/0227 takes precedence
• CPC Class Codes: C23C 16/0245 by etching with a plasma
• CPC Class Codes: C23C 16/22 characterised by the deposition of inorganic material, other than metallic material
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/405 of refractory metals or yttrium
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02315 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31604 : Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 : on a silicon body
• CPC Class Codes: H01L 21/32055 : Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material. Preferably less than 10 Å of the bulk material incorporates the excited species, which can include fluorine, chlorine and particularly nitrogen excited species.

Claims

1. A method of depositing a film over a surface in a partially fabricated integrated circuit, the surface comprising a top surface of a transistor gate dielectric layer, the method comprising:

exposing the surface to products of a plasma, thereby modifying termination of the surface without significantly affecting bulk properties beneath the surface; and

depositing a silicon-containing layer thereover after modifying the surface termination, the silicon-containing layer comprising polycrystalline silicon germanium alloy (poly-SiGe).

2. The method of claim 1, wherein a germanium content at an interface with the transistor gate dielectric layer and the poly-SiGe layer is between about 20% and 50%.

3. The method of claim 1, wherein the transistor gate dielectric layer comprises a high dielectric material.

4. The method of claim 1, wherein depositing the silicon-containing layer comprises simultaneously flowing a silicon source gas and germane.

5. The method of claim 1, wherein exposing comprises providing a flow of radicals from a remote plasma source to the surface.

6. The method of claim 5, wherein the flow of radicals is stopped prior to depositing.

7. The method of claim 1, wherein the products of the plasma comprise nitrogen excited species, the transistor gate dielectric layer has a dielectric constant greater than about 4, and the transistor gate dielectric layer comprises less than 10% atomic nitrogen at about 10 Å

from the surface.

8. The method of claim 1, wherein exposing does not deposit a layer greater than about one atomic monolayer.

9. A method of depositing a film over a metal oxide surface in a partially fabricated integrated circuit, comprising:

exposing the metal oxide surface to products of a plasma, thereby;

modifying a termination of the metal oxide surface without significantly affecting bulk properties beneath the metal oxide surface, and without depositing a layer greater than about one atomic monolayer, and

converting a metal oxide beneath the metal oxide surface to metal oxynitride no more than about 10 Å

from the surface; and

depositing a layer thereover after modifying the metal oxide surface termination.

10. The method of claim 9, wherein depositing a layer comprises depositing a polycrystalline silicon germanium (poly-SiGe) layer over the metal oxide surface after modifying the metal oxide surface termination.

11. The method of claim 10, wherein a germanium content at an interface with the metal oxide surface and the poly-SiGe layer is between about 20% and 50%.

12. The method of claim 10, wherein depositing the poly-SiGe layer comprises depositing a layer of silicon-germanium by chemical vapor deposition.

13. The method of claim 10, wherein depositing the poly-SiGe layer comprises simultaneously flowing a silicon source gas and a germane.

14. The method of claim 9, wherein exposing comprises providing a flow of radicals from a remote plasma source to the surface.

15. The method of claim 14, wherein the flow of radicals is stopped before depositing.

16. The method of claim 9, wherein the products of the plasma comprise nitrogen excited species, the metal oxide has a dielectric constant greater than about 4, and the metal oxide comprises less than 10 atomic % nitrogen at about 10 Å

from the surface.

17. The method of claim 9, further comprising exposing a substrate surface to a source of nitrogen excited species before forming the metal oxide thereover.

18. The method of claim 17, wherein exposing the substrate to a source of nitrogen excited species forms less than about 10 Å

of silicon oxynitride.

19. The method of claim 9, wherein the metal oxide beneath the metal oxide surface comprises a high dielectric material.