Method and circuit for providing interface signals between integrated circuits

• US 6,615,027 B1
• Filed: 01/21/2000
• Issued: 09/02/2003
• Est. Priority Date: 01/21/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sani, Mehdi H., Shahrokhinia, Sassan, Sahota, Gurkanwal
• Primary Examiner(s): VUONG, QUOCHIEN B
• Application Number:
  US09/489,231
• Time in Patent Office: 1,320 Days
• Field of Search: 455/91, 455/93, 455/95, 455/575, 379/399.01, 341/154, 341/155, 341/144, 341/135, 341/126
• US Class Current: 455/91
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.

Claims

1. Circuitry to generate an interface signal between a first integrated circuit and a second integrated circuit comprising:

a reference circuit configured to provide a reference signal;

an interface circuit implemented on the first integrated circuit and operatively coupled to the reference circuit, the interface circuit configured to receive the reference signal and a data input and to generate the interface signal in response thereto; and

a circuit element implemented on the second integrated circuit and operatively coupled to the interface circuit, the circuit element configured to receive the interface signal and provide an output signal in response,

wherein the interface signal is a differential current signal.

2. The circuitry of claim 1, wherein the reference circuit is implemented on the second integrated circuit.

3. The circuitry of claim 1, further comprising:

at least one capacitor coupled between the differential current signal.

4. The circuitry of claim 1, wherein the interface signal represents an analog inphase (I) or quadrature (Q) baseband signal in a quadrature transmitter.

5. The circuitry of claim 1, wherein the reference signal is a voltage related to a bandgap voltage.

6. The circuitry of claim 1, wherein the reference signal is a current generated from a reference voltage and a resistor.

7. The circuitry of claim 6, wherein the output signal is a voltage signal, and wherein the resistor is external to the first and second integrated circuits.

8. The circuitry of claim 6, wherein the output signal is a current signal, and wherein the resistor is implemented on the second integrated circuit.

9. The circuitry of claim 6, wherein the interface circuit includes

a current mirror configured to receive the reference signal and to provide two or more mirror paths, and

a switch array coupled to the current mirror, the switching array configured to receive and decode the data input and to direct current from a set of selected mirror paths to an output of the switch array.

10. The circuitry of claim 1, wherein the data input comprises at least four bits of resolution.

11. The circuitry of claim 10, wherein the data input comprises at least eight bits of resolution.

12. The circuitry of claim 1, wherein the interface circuit is oversampled by an oversampling ratio of two or greater.

13. The circuitry of claim 12, wherein the oversampling ratio is 16 or greater.

14. The circuitry of claim 1, wherein the circuit element is a variable gain amplifier (VGA).

15. The circuitry of claim 1, wherein the circuit element is a modulator.

16. The circuitry of claim 15, wherein the modulator includes

a pair of current sources coupled to the interface signal, and

a pair of cross-coupled differential amplifiers, each differential amplifier coupled to a respective current source, the differential amplifiers configured to receive a carrier signal and to generate the output signal based, in part, on the carrier signal and the interface signal.

17. The circuitry of claim 16, wherein each current source in the modulator provides a bias current that is related to the reference signal.

18. A transmitter comprising the circuitry of claim 1.

19. A transmitter in a CDMA cellular telephone comprising the circuitry of claim 1.

20. Circuitry in a transmitter comprising:

a first interface circuit implemented on a first integrated circuit, the first interface circuit configured to receive a first data input and provide a first differential current signal; and

a modulator implemented on a second integrated circuit and operatively coupled to the first interface circuit, the modulator configured to receive the first differential current signal and a carrier signal and to generate an output signal in response thereto.

21. The circuitry of claim 20, further comprising:

a second interface circuit implemented on the first integrated circuit, the second interface circuit configured to receive a second data input and provide a second differential current signal,

wherein the modulator is further configured to receive the second differential current signal and to generate the output signal in response to the second differential current signal.

22. The circuitry of claim 21, wherein the first and second data inputs correspond to inphase (I) and quadrature (Q) baseband signals in a quadrature transmitter.

23. The circuitry of claim 21, further comprising:

a capacitor coupled between each of the first and second differential current signals.

24. The circuitry of claim 21, wherein each of the first and second data inputs has eight or more bits of resolution.

25. The circuitry of claim 21, wherein the first and second interface circuits are operated at an oversampled rate relative to a rate of the first and second data inputs.

26. The circuitry of claim 25, wherein the oversampled rate is sixteen or greater.

27. The circuitry of claim 20, further comprising:

a reference circuit implemented on the second integrated circuit and configured to provide a reference signal,

wherein the first interface circuit couples to the reference circuit and is further configured to receive the reference signal and to generate the first differential current signal based, in part, on the reference signal.

28. The circuitry of claim 27, wherein the reference signal is a current generated based on a reference voltage.

29. A transmitter in a cellular telephone comprising:

a digital processor implemented on a first integrated circuit and configured to provide digital inphase (I) and quadrature (Q) baseband signals;

first and second interface circuits implemented on the first integrated circuit and coupled to the digital processor, each interface circuit configured to receive a respective digital baseband signal and provide an analog baseband signal, wherein each quantized analog baseband signal comprises at least four bits of resolution and is implemented as a differential current signal; and

a modulator implemented on a second integrated circuit and operatively coupled to the first and second interface circuits, the modulator configured to receive and modulate the analog baseband signals with a carrier signal to provide a modulated output signal.

30. The transmitter of claim 29, further comprising:

a reference circuit implemented on the second integrated circuit and configured to provide a reference signal,

wherein each interface circuit couples to the reference circuit and is further configured to receive the reference signal, and wherein the analog baseband signals are further generated based, in part, on the reference signal.

31. A device comprising:

an interface circuit formed on a first integrated circuit (IC) for generating a differential current signal responsive to a reference signal and to a digital data input; and

a circuit element formed on a second IC for generating an output signal on the basis of the differential current signal.

32. The device of claim 31, wherein the device is a transmitter.

33. The device of claim 32, wherein the transmitter is a quadrature transmitter.

34. The device of claim 31, wherein the device is a CDMA telephone.

35. The device of claims 31, 32, or 34, wherein the reference signal is generated by a reference circuit on the second IC.

36. The device of claims 31, 32, or 34, further comprising a reference circuit for generating the reference signal.

37. The device of claims 31, 32, or 34, further comprising at least one capacitor coupled between the differential current signal.

38. The device of claims 31, 32, or 34, wherein the digital data input is at least one of an analog inphase (I) and a quadrature (Q) baseband signal.

39. The device of claims 31, 32, or 34, wherein the reference signal is a voltage reference signal.

40. The device of claim 39, wherein the voltage reference signal is generated on the bas of a bandgap reference voltage.

41. The device of claims 31, 32, or 34, wherein the reference signal is a current generated from a reference voltage and a resistor.

42. The device of claim 41, wherein the output signal is a voltage signal and the resistor is external to the first and second ICs.

43. The device of claim 41, wherein the output signal is a current signal and the resistor is implemented on the second IC.

44. The device of claims 31, 32, or 34, wherein the interface circuit includes a current mirror for generating at least two mirror paths using the reference signal and a switch array for decoding the digital data input and for directing current from selected ones of the mirror paths to generate the differential current signal.

45. The device of claims 31, 32, or 34, wherein the digital data input is at least a four bit digital data input.

46. The device of claims 31, 32, or 34, wherein the digital data input is an oversampled digital data signal.

47. The device of claims 31, 32, or 34, wherein the circuit element is any of a variable gain amplifier (VGA), mixer, and power amplifier (PA) driver.

48. The device of claims 31, 32, or 34, wherein the circuit element is a modulator.

49. The device of claim 48, wherein the modulator includes a pair of current sources coupled to the differential current signal, and a pair of cross-coupled differential amplifiers, each differential amplifier coupled to a respective current source, the differential amplifiers operating to receive a carrier signal and to generate the output signal based, in part, on the carrier signal and the differential current signal.

50. The device of claim 49, wherein each current source in the modulator provides a bias current that is related to the reference signal.

51. The device of claim 48, wherein the modulator performs direct up conversion.

52. A device comprising:

an interface circuit for generating a differential current signal, responsive to a reference signal and to a digital data input and adapted for external capacitive filtering between the differential current signal; and

a circuit element for generating an output signal on the basis of the differential current signal.

53. The device of claim 52, wherein the device is a transmitter.

54. The device of claim 53, wherein the transmitter is a quadrature transmitter.

55. The device of claim 52, wherein the device is a CDMA telephone.

56. The device of claims 52, 53, or 55, wherein the digital data input is at least one of an analog inphase (I) and a quadrature (Q) baseband signal.

57. The device of claims 52, 53, or 55, wherein die interface circuit includes a cement mirror for generating at least two mirror paths using the reference signal and a switch army for decoding the digital data input and for directing current from selected ones of the mirror paths to generate the differential current signal.

58. The device of claims 52, 53, or 55, wherein the circuit element is any of a variable gain amplifier (VGA), mixer, and power amplifier (PA) driver.

59. The device of claims 52, 53, or 55, wherein the circuit element is a modulator.

60. The device of claim 54, wherein the modulator includes a pair of current sources coupled to the differential current signal, and a pair of cross-coupled differential amplifiers, each differential amplifier coupled to a respective current source, the differential amplifiers operating to receive a carrier signal and to generate the output signal based, in part, on the carrier signal and the differential current signal.

61. The device of claim 60, wherein each current source in the modulator provides a bias current that is related to the reference signal.

62. The device of claim 60, wherein the modulator performs direct up conversion.

63. An analog integrated circuit (IC) adapted for use in a transmit signal path of a communication device, and responsive to an input differential current signal generated externally as a function of a reference signal and a digital data input, the analog IC comprising:

a reference circuit for generating the reference signal; and

a circuit element for generating an output signal on the basis of the differential current signal.

64. The analog integrated circuit of claim 63, wherein the reference signal is a voltage reference signal.

65. The analog integrated circuit of claim 64, wherein the voltage reference signal is generated on the basis of a bandgap reference voltage.

66. The analog integrated circuit of claim 63, wherein the reference signal is a current generated from a reference voltage and a resistor.

67. The analog integrated circuit of claim 66, wherein the output signal is a voltage signal and the resistor is external to the analog integrated circuit.

68. The analog integrated circuit of claim 66, wherein the output signal is a current signal and the resistor is implemented on the analog integrated circuit.

69. The analog integrated circuit of claim 63, wherein the circuit element is any of a variable gain amplifier (VGA), mixer, and power amplifier (PA) driver.

70. The analog integrated circuit of claim 63, wherein the circuit element is a modulator.

71. The analog integrated circuit of claim 70, wherein the modulator includes a pair of current sources coupled to the differential current signal, and a pair of cross-coupled differential amplifiers, each differential amplifier coupled to a respective current source, the differential amplifiers operating to receive a carrier signal and to generate the output signal based, in part, on the carrier signal and the differential current signal.

72. The analog integrated circuit of claim 71, wherein each current source in the modulator provides a bias current that is related to the reference signal.

73. The analog integrated circuit of claim 70, wherein the modulator performs direct up conversion.

74. An integrated circuit (IC) comprising:

a digital processor generating a digital data input; and

at least one interface circuit responsive to a reference signal for generating a differential current signal responsive to a reference signal and to the digital data input.

75. The integrated circuit of claim 74, wherein the at least one interface circuit includes a current mirror for generating at least two mirror paths using the reference signal and a switch array for decoding the digital data input and for directing current from selected ones of the mirror paths to generate the differential current signal.

76. The integrated circuit of claim 75, wherein the digital data input is at least a four bit digital data input.

77. The integrated circuit of claim 76, wherein the digital data input is an oversampled digital data signal.

78. A method comprising:

generating a reference signal;

providing the reference signal to a first circuit;

receiving a digital data input at the first circuit;

generating a differential current signal in the first circuit based, in part, on the digital data input and the reference signal;

providing the differential current signal from the first circuit to a second circuit;

receiving the differential current signal at the second circuit; and

generating an output signal from a circuit element in the second circuit, the output signal being based at least in part on the differential current signal.

79. The method of claim 78, wherein the reference signal is a current generated from a reference voltage.

80. The method of claim 78, further comprising filtering the differential current signal.

81. The method of claim 78, further comprising providing a signal related to the reference signal to the circuit element, wherein the output signal is further generated based, in part, on the signal related to the reference signal.

82. A system comprising:

means, formed on a first integrated circuit (IC), for generating a differential current signal responsive to a reference signal and to a digital data input; and

means, formed on a second IC, for generating an output signal on the basis of the differential current signal.

83. A system comprising:

means for generating a differential current signal, responsive to a reference signal and to a digital data input and adapted for external capacitive filtering between the differential current signal; and

means for generating an output signal on the basis of the differential current signal.

84. An analog integrated circuit (IC) adapted for use in a transmit signal path of a communication device, and responsive to an input differential current signal generated externally as a function of a reference signal and a digital data input, the analog IC comprising:

means for generating the reference signal; and

means for generating an output signal on the basis of the differential signal.

85. An integrated circuit (IC) comprising:

means for generating a digital data input; and

at least one interface circuit means responsive to a reference signal for generating a differential current signal responsive to a reference signal and to the digital data input.