Transparently partitioned communication bus for multi-port bridge for a local area network

• US 6,617,879 B1
• Filed: 03/19/1999
• Issued: 09/09/2003
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Chung, David
• Primary Examiner(s): LE, DON P
• Application Number:
  US09/272,894
• Time in Patent Office: 1,635 Days
• Field of Search: 326/37-41, 326/82, 326/83, 326/86, 370/235, 370/357, 370/360, 370/362, 370/364, 370/401, 370/413, 370/229, 370/230
• US Class Current: 326/82
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40143 involving priority mechanisms hybrid switching fabrics H04L12/6402; intermediate storage or scheduling H04L49/90; time-division multiplex systems H04J3/00
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/135 by jamming the transmission media
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

A transparently partitioned communication bus for interconnecting the ports of a multi-port bridge for a local area network. The communication bus is partitioned into a plurality of bus segments, each segment coupled to one or more ports of the multi-port bridge and including a same number (n) of signal lines. A controller pre-charges each signal line to a logic high voltage level by activating pre-charge transistors coupled between a voltage supply and a plurality of diodes, each diode coupled to a corresponding one of the signal lines. The pre-charging operation includes all the signal lines. The ports request access to the partitioned bus. A port having been granted access to the partitioned bus applies data to its associated bus segment. The transparent controller then senses the data applied by the port via sense lines. Then, the transparent controller replicates this data to each other bus segment by discharging appropriate ones of the signal lines of each other bus segment via appropriate ones of a plurality of discharge transistors. The discharge transistors are coupled to between each signal line and ground. This technique results in the data being quickly replicated to the other bus segments. Accordingly, the bus is “transparently” partitioned such that the bus segments, in conjunction with the controller, form a single logical bus by which the ports communicate data. A principle advantage is that the entire bus cycle can be made shorter than a bus cycle for a non-partitioned bus.

Claims

1. An apparatus having a partitioned bus for transferring data, the apparatus comprising:

a. a first bus segment having a first plurality of (n) signal lines;

b. a second bus segment having a second plurality of (n) signal lines;

c. conditioning means coupled to the first bus segment for conditioning a logic level of each signal line of the first bus segment according to data to be transferred;

d. sensing means coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;

e. pre-charging means coupled to the second bus segment for pre-charging each signal line of the second bus segment; and

f. dis-charging means coupled to the second bus segment for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment.

2. The apparatus according to claim 1 further comprising receiving means coupled to the second bus segment for receiving the data.

3. The apparatus according to claim 1 wherein the conditioning means requests access to the partitioned bus prior to conditioning the logic level of signal lines of the first bus segment according to the data.

4. The apparatus according to claim 1 wherein the sensing means senses the logic level of each signal line of the first bus segment simultaneously as the conditioning means conditions the logic level of signal lines of the first bus segment according to the data.

5. The apparatus according to claim 1 wherein the dis-charging means dis-charges a signal line of the second bus segment when a voltage level of a corresponding one of the signal lines of the first bus segment falls below a predetermined threshold.

6. A multi-port bridge having a partitioned bus for transferring data between ports of the multi-port bridge, the multi-port bridge comprising:

a. a first bus segment having a first plurality of (n) signal lines;

b. a second bus segment having a second plurality of (n) signal lines;

c. a controller coupled to the first bus segment for sensing a logic level of each signal line of the first bus segment;

d. a transistor coupled to be controlled by the controller for pre-charging each signal line of the second bus segment; and

e. a plurality of transistors coupled to be controlled by the controller for dis-charging selected ones of the signal lines of the second bus segment so as to replicate logic levels of the corresponding signal lines of the first bus segment.

7. The multi-port bridge according to claim 6 further comprising a plurality of diodes coupled to the transistor, one diode for each signal line of the second bus segment, wherein each signal line of the second bus segment is pre-charged through the corresponding one of the diodes.

8. The multi-port bridge according to claim 6 further comprising a first port coupled to the first bus segment for conditioning the logic level of signal lines of the first bus segment according to data to be transferred from the first port.

9. The multi-port bridge according to claim 8 further comprising a second port coupled to the second bus segment for receiving the data transferred from the first port.

10. The multi-port bridge according to claim 8 further comprising a buffer memory coupled to the second bus segment for receiving the data transferred from the first port.

11. The multi-port bridge according to claim 8 further comprising a look-up table coupled to the first port for correlating destination addresses of packets received by the first port to identifications of appropriate destination ports for the packets.

12. The multi-port bridge according to claim 8 wherein the first port requests access to the partitioned bus prior to conditioning the logic level of signal lines of the first bus segment according to the data to be transferred from the first port.

13. The multi-port bridge according to claim 8 wherein the controller senses the logic level of each signal line of the first bus segment simultaneously as the first port conditions the logic level of signal lines of the first bus segment according to the data to be transferred from the first port.

14. The multi-port bridge according to claim 13 wherein the controller dis-charges a signal line of the second bus segment when a voltage level of a corresponding one of the signal lines of the first bus segment falls below a predetermined threshold.

15. A method of transferring data between ports of a multi-port bridge, the method comprising steps of:

a. conditioning a first bus segment having a first plurality of (n) signal lines according to logic levels of data to be transferred by a first port;

b. pre-charging a second bus segment having a second plurality of (n) signal lines whereby each signal line of each of the second bus segment attains a logic high voltage level;

c. sensing a logic level of each signal line of the first bus segment; and

d. dis-charging selected ones of the signal lines of the second bus segment to a logic low voltage level so as to replicate the logic levels of the first bus segment.

16. The method according to claim 15 wherein the step of pre-charging comprises a step of forward biasing each of a plurality of diodes, one diode coupled to each signal line of the second bus segment.

17. The method according to claim 15 further comprising a step of pre-charging the first bus segment prior to performing the step of conditioning.

18. The method according to claim 15 further comprising a step of receiving the data from the second bus segment into a second port.

19. The method according to claim 15 further comprising a step of receiving the data from the second bus segment into a buffer memory.

20. The method according to claim 15 further comprising a step of correlating a destination address of packets received by the first port to an identification of an appropriate destination port for the packet.

21. The method according to claim 15 further comprising a step of requesting access to the partitioned bus prior to performing the step of conditioning.

22. The method according to claim 15 wherein the step of sensing the logic level of each signal line of the first bus segment is performed simultaneously with the step of conditioning the logic level of signal lines of the first bus segment.

23. The method according to claim 22 wherein the step of dis-charging a signal line of the second bus segment is performed upon a voltage level of a corresponding one of the signal lines of the first bus segment falling below a predetermined threshold.

24. A multi-port bridge having a partitioned bus for transferring data between ports the multi-port bridge, the multi-port bridge comprising:

a. a first bus segment having a first plurality of (n) signal lines;

b. a second bus segment having a second plurality of (n) signal lines;

c. a controller coupled to the first bus segment via a first plurality of (n) sense lines for sensing a respective logic level of each signal line of the first bus segment and coupled to the second bus segment via a second plurality of (n) sense lines for sensing a respective logic level of each signal line of the second bus segment;

d. a first plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the first bus segment and the anodes of the first plurality of diodes are each selectively coupled to a supply voltage under control of the controller;

e. a second plurality of diodes, each having an anode and a cathode, wherein the cathodes of the first plurality of diodes are each coupled to a respective one of the signal lines of the second bus segment and the anodes of the second plurality of diodes are each selectively coupled to a first supply voltage level under control of the controller;

f. a first plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the first plurality of transistors are each coupled to a second supply voltage level, and wherein the output terminals of the first plurality of transistors are each coupled to a respective one of the signal lines of the first bus segment and further wherein the control terminals of the first plurality of transistors are each coupled to the controller; and

g. a second plurality of transistors, each having an input terminal, an output terminal and a control terminal, wherein the input terminals of the second plurality of transistors are each coupled to the second supply voltage level, and wherein the output terminals of the second plurality of transistors are each coupled to a respective one of the signal lines of the second bus segment and further wherein the control terminals of the second plurality of transistors are each coupled to the controller.

25. The multi-port bridge according to claim 24 further comprising a first transistor having an input terminal, an output terminal and a control terminal wherein the input terminal is coupled to the first supply voltage level, the output terminal is coupled to the anode of each diode of the first plurality of diodes and the control terminal is coupled to the controller.

26. The multi-port bridge according to claim 25 further comprising a second transistor having an input terminal, an output terminal and a control terminal wherein the input terminal is coupled to the first supply voltage level, the output terminal is coupled to the anode of each diode of the second plurality of diodes and the control terminal is coupled to the controller.

27. The multi-port bridge according to claim 24 further comprising a first port coupled to the first bus segment for applying data to be communicated via the partitioned bus to the first bus segment and for receiving data communicated via the partitioned bus from the first bus segment wherein the first port is for coupling a first network segment having one or more nodes to the multi-port bridge.

28. The multi-port bridge according to claim 27 further comprising a second port coupled to the second bus segment for applying data to be communicated via the partitioned bus to the second bus segment and for receiving data communicated via the partitioned bus from the second bus segment wherein the second port is for coupling a second network segment having one or more nodes to the multi-port bridge.

29. The multi-port bridge according to claim 28 wherein the controller replicates logic levels from first bus segment to the second bus segment by activating selected ones of the second plurality of transistors.