Digital-to-analog converter using pseudo-random sequences and a method for using the same

• US 6,617,990 B1
• Filed: 03/06/2002
• Issued: 09/09/2003
• Est. Priority Date: 03/06/2002
• Status: Expired due to Fees

• Current Assignee: MeshNetworks, Inc. (Motorola Solutions, Inc.)
• Original Assignee: MeshNetworks, Inc. (Motorola Solutions, Inc.)
• Inventors: Alapuranen, Pertti O., Lorenzo-Luaces, Eduardo, Strutt, Guénaël T.
• Primary Examiner(s): JeanPierre, Peguy
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US10/091,032
• Time in Patent Office: 552 Days
• Field of Search: 341/144, 341/118, 341/120, 395/267
• US Class Current: 341/144
• CPC Class Codes: H03M 1/04 using stochastic techniques
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence

Abstract

A system and method for providing discrete analog voltage levels. The system and method employs a pseudo-random sequence generator for generating random-sequences of binary values, namely zeros and ones, based on a digital input. The pseudo-random sequence serves to modulate a current source whose output is integrated to develop a constant discrete analog voltage output. This method reduces spurious frequency interference on the circuit. The system and method can be employed in a node of a wireless ad-hoc communications network.

Claims

1. A system for providing at least one analog voltage level, comprising:

a pseudo-random sequence generator, adapted to generate at least one pseudo-random sequence of binary values; and

an integrator, adapted to provide an analog voltage having a value based on a relationship between the values of a plurality of bits of said pseudo-random sequence represented by the following formula;

2. A system as claimed in claim 1, wherein:

said integrator includes a capacitor which is adapted to develop said analog voltage.

3. A system as claimed in claim 1, wherein:

said integrator includes a current source, which is adapted to be modulated by said pseudo-random sequence to produce current pulses from which said analog voltage is produced.

4. A system as claimed in claim 3, wherein:

said integrator further includes a capacitor, which is adapted to develop said analog voltage based on said current pulses.

5. A system as claimed in claim 1, wherein:

said relationship represents a number of a type of binary values in said sequence in relation to a number of another type of binary values in said sequence.

6. A system as claimed in claim 5, wherein:

said type of binary values are high values, and said another type of binary values are low values.

7. A system as claimed in claim 1, wherein:

said pseudo-random sequence generator is adapted to generate a plurality of pseudo-random sequences of binary values; and

said integrator is adapted to provide respective analog voltages, each having a respective value based on a respective said relationship between the values of a plurality of bits of each said respective pseudo-random sequence.

8. A system as claimed in claim 1, wherein:

said pseudo-random sequence generator and said integrator are employed in a node of an ad-hoc communications network.

9. A method for providing at least one analog voltage level, comprising:

operating a pseudo-random sequence generator to generate at least one pseudo-random sequence of binary values; and

integrating said binary sequence to provide an analog voltage having a value based on a relationship between the values of a plurality of bits of said pseudo-random sequence represented by the following formula;

10. A method as claimed in claim 9, wherein:

said integrating includes modulating a current source by said pseudo-random sequence to produce current pulses from which said analog voltage is produced.

11. A method as claimed in claim 10, wherein:

said integrating further includes inputting said current pulses to a capacitor, which is adapted to develop said analog voltage based on said current pulses.

12. A method as claimed in claim 9, wherein:

said relationship represents a number of a type of binary values in said sequence in relation to another type of binary values in said sequence.

13. A method as claimed in claim 12, wherein:

said type of binary values are high values and said another type of binary values are low values.

14. A method as claimed in claim 9, wherein:

said operating operates said pseudo-random sequence generator to generate a plurality of pseudo-random sequences of binary values; and

said integrating provides respective analog voltages, each having a respective value based on a respective said relationship between the values of a plurality of bits of each said respective pseudo-random sequence.

15. A method as claimed in claim 9, wherein:

said operating and integrating are performed in a node of an ad-hoc communications network.

23. A method as claimed in claim 12, wherein:

said integrating includes modulating a current source by said pseudo-random sequence to produce current pulses from which said analog voltage is produced.

24. A method as claimed in claim 23, wherein:

said integrating further includes inputting said current pulses to a capacitor, which is adapted to develop said analog voltage based on said current pulses.

25. A method as claimed in claim 12, wherein:

said operating operates said pseudo-random sequence generator to generate a plurality of pseudo-random sequences of binary values; and

said integrating provides respective analog voltages, each having a respective value based on a characteristic of each said respective pseudo-random sequence.

26. A method as claimed in claim 12, wherein:

said operating and integrating are performed in a node of an ad-hoc communications network.

16. A system for providing at least one analog voltage level, comprising:

a pseudo-random sequence generator, adapted to generate at least one pseudo-random sequence of binary values; and

an integrator, adapted to provide an analog voltage having a value based on a characteristic of said pseudo-random sequence represented by the following formula;

17. A system as claimed in claim 16, wherein:

said integrator includes a capacitor which is adapted to develop said analog voltage.

18. A system as claimed in claim 16, wherein:

said integrator includes a current source, which is adapted to be modulated by said pseudo-random sequence to produce current pulses from which said analog voltage is produced.

19. A system as claimed in claim 18, wherein:

said integrator further includes a capacitor, which is adapted to develop said analog voltage based on said current pulses.

20. A system as claimed in claim 16, wherein:

said pseudo-random sequence generator is adapted to generate a plurality of pseudo-random sequences of binary values; and

said integrator is adapted to provide respective analog voltages, each having a respective value based on a characteristic of each said respective pseudo-random sequence.

21. A system as claimed in claim 16, wherein:

said pseudo-random sequence generator and said integrator are employed in a node of an ad-hoc communications network.

22. A method for providing at least one analog voltage level, comprising:

operating a pseudo-random sequence generator to generate at least one pseudo-random sequence of binary values; and

integrating said binary sequence to provide an analog voltage having a value based on a characteristic of said pseudo-random sequence represented by the following formula;