System and method for testing a circuit implemented on a programmable logic device

• US 6,618,686 B2
• Filed: 05/14/1999
• Issued: 09/09/2003
• Est. Priority Date: 05/14/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Allamsetty, Chakravarthy K.
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): PRETLOW, DEMETRIUS R
• Application Number:
  US09/311,628
• Publication Number:
  US 20030078752A1
• Time in Patent Office: 1,579 Days
• Field of Search: 702/120, 702/117, 716/4, 716/16, 324/755, 324/73.1, 324/763, 324/142, 324/74, 324/754
• US Class Current: 702/120
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/31915 In-circuit Testers

Abstract

A system and method for testing a circuit implemented on a programmable logic device. A host processor is coupled to the programmable logic device via an interface device, which has a plurality of signal pins for configuring the programmable logic device. Selected pins of the interface device are connected to selected input pins of the programmable logic device. Test vectors from the host processor are applied to the selected input pins of the programmable logic device via the interface device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.

Claims

1. A method for testing a circuit implemented on a programmable logic device using a host processor coupled to the programmable logic device via an interface device containing at least one electronic device, the interface device having a plurality of signal pins for configuring the programmable logic device, comprising:

connecting selected pins of the interface device containing at least one electronic device to selected input pins of the programmable logic device;

applying test vectors from the host processor to the selected input pins of the programmable logic device via the interface device containing at least one electronic device, each test vector including one or more signal states to be applied to the programmable logic device; and

analyzing states of signals appearing on output pins of the programmable logic device.

2. The method of claim 1 wherein the step of analyzing states of signals appearing on output pins of the programmable logic device comprises comparing signals on the output pins to expected output signals.

3. The method of claim 1, further comprising:

connecting selected pins of the interface device to associated configuration pins of the programmable logic device; and

configuring the programmable logic device with a circuit design downloaded from the host processor to the programmable logic device via the interface device.

4. The method of claim 1, further comprising reading signal states from selected output pins of the programmable logic device to the host processor via the interface device.

5. The method of claim 1, wherein a logic analyzer is connected to one or more output pins of the programmable logic device, and further comprising viewing the signal states on the one or more output pins of the programmable logic device.

6. The method of claim 1, further comprising issuing from a test program executing on the host processor a programming interface write command having the test vector and a specification of the pins on which to apply the test vector.

7. The method of claim 6, wherein the interface device includes a plurality of ports, each port including a plurality of pins, and further comprising specifying in the write command the port having the pins on which the test vector is to be applied.

8. The method of claim 7, further comprising issuing from the test program a programming interface select-port-pins command having a port identifier and a bit-mask for enabling writing of data to specified pins of a specified port.

9. The method of claim 1, further comprising issuing from a test program executing on the host processor a programming interface read command having a specification of pins from which to read output signals.

10. The method of claim 6, wherein the interface device includes a plurality of ports, each port including a plurality of pins, and further comprising specifying in the read command the port having the pins on which the signals are to be read.

11. A system for testing a circuit implemented on a programmable logic device having input and output pins, comprising:

a host data processing system configured and arranged to configure the programmable logic device during a configuration process, and to apply input test signals to selected pins of the programmable logic device during a test process;

an interface device comprising a microcontroller and a RAM, the interface device having pins arranged to be connected to the programmable logic device, wherein selected pins of the interface device are used by the host for predetermined functions during configuration and for test signals during the test process.

12. The system of claim 11, wherein the host is further configured and arranged to read signals output from the programmable logic device via selected pins of the interface device.

13. The system of claim 12, wherein the interface device includes a plurality of ports, each having a respective plurality of pins.

14. The system of claim 13, wherein the host is further configured and arranged to issue a write command to the interface device which specifies the port and states of signals to apply to pins of the port.

15. The system of claim 14, wherein the host is further configured and arranged to issue a read command to the interface device which specifies the port and pins of the port from which states of signals are obtained.

16. A system for testing a circuit implemented on a programmable logic device having input and output pins, comprising:

a host data processing system configured and arranged to configure the programmable logic device during a configuration process, and to apply input test signals to selected pins of the programmable logic device during a test process;

an interface device having pins arranged to be connected to the programmable logic device, the interface device including electronic circuits to drive signals to the programmable logic device during configuration of the programmable logic device, and electronic circuits to receive signals from the programmable logic device during testing of the programmable logic device.