Method of fabricating a metal-insulator-metal (MIM) capacitor

• US 6,620,701 B2
• Filed: 10/12/2001
• Issued: 09/16/2003
• Est. Priority Date: 10/12/2001
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Ning, Xian J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US09/977,004
• Publication Number:
  US 20030073282A1
• Time in Patent Office: 704 Days
• Field of Search: 438/244, 438/250, 438/253, 438/387, 438/393, 438/396, 438/381, 257/306, 257/301, 257/27.048, 257/27.092
• US Class Current: 438/396
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a metal-insulator-metal capacitor (MIMCap) (36) including first conductive lines (15), capacitor dielectric (26) and second conductive lines (28), the MIMCap (36) including horizontal capacitive portions (32) and vertical capacitive portions (34). The method includes forming first conductive lines (15) in a first insulating layer (14) of a wafer (10), depositing a second insulating layer (22), depositing a resist, removing portions of the resist, removing exposed portions of the second insulating layer (22) and portions of the first insulating layer (14), removing the remaining resist, and then depositing a capacitor dielectric (26) and second conductive lines (28).

Claims

1. A method of fabricating a metal-insulator-metal capacitor (MIMCap), comprising:

providing a wafer having a workpiece;

depositing a first insulating layer over the workpiece;

forming a plurality of first conductive lines within the first insulating layer, the first conductive lines comprising a first conductive material;

depositing a second insulating layer;

depositing a resist over the second insulating layer;

patterning the resist with a predetermined pattern;

removing portions of the resist to expose portions of the second insulating layer;

removing at least the exposed second insulating layer and portions of the first insulating layer, leaving portions of the first conductive lines exposed;

removing the remaining resist;

depositing a capacitor dielectric over the first conductive lines; and

depositing a second conductive material over the capacitor dielectric to form second conductive lines.

2. The method according to claim 1 wherein portions of the first conductive lines, capacitor dielectric and the second conductive lines form a MIMCap, and wherein portions of the first and second conductive lines comprise plates of the MIMCap, the MIMCap plates having horizontal and vertical portions.

3. The method according to claim 2, further comprising:

coupling together portions of the first conductive lines; and

coupling together portions of the second conductive lines.

4. The method according to claim 2 further comprising:

simultaneously forming interconnect lines in a metallization layer, when forming the first conductive lines of the MIMCap.

5. The method according to claim 1 further comprising:

depositing a cap layer over the first insulating layer and the first conductive lines; and

removing portions of the cap layer when removing the exposed second and first insulating layers.

6. The method according to claim 5, wherein depositing a cap layer comprises depositing silicon nitride.

7. The method according to claim 1, wherein removing the exposed first and second insulating layers comprises a reactive ion etch (RIE) process.

8. The method according to claim 7, wherein the RIE comprises an etch process selective to the first conductive line material.

9. The method according to claim 1, wherein forming a plurality of first conductive lines within the first insulating layer comprises a dual or single damascene process.

10. The method according to claim 9, wherein the first conductive material comprises copper.

11. The method according to claim 10, wherein forming the first conductive lines comprises:

forming a plurality of trenches within the first insulating layer, the first insulating layer having a top surface;

depositing a copper liner the first insulating layer and within the trenches;

forming a copper seed layer over the copper liner;

filling the trenches with the first conductive material; and

chemically-mechanically polishing the wafer to remove the copper liner, copper seed layer, and conductive material from the first insulating layer top surface.

12. The method according to claim 1 wherein forming the second conductive lines comprises forming tungsten lines.

13. The method according to claim 1 wherein forming the first and second insulating layers comprise forming inter-level dielectric layers.

14. The method according to claim 1, further comprising depositing a third insulating layer over the second insulating layer and the second conductive lines.

15. The method according to claim 1, wherein depositing the capacitor dielectric comprises depositing silicon nitride.

16. A method of fabricating a vertical/horizontal metal-insulator-metal capacitor (MIMCap), comprising:

providing a wafer having a workpiece;

depositing a first insulating layer over the workpiece;

forming a plurality of trenches within the first insulating layer;

filling the trenches with a first conductive material to form first conductive lines within the first insulating layer;

depositing a cap layer over the first conductive lines and first insulating layer;

depositing a second insulating layer over the cap layer;

depositing a resist over the second insulating layer;

patterning the resist with a predetermined pattern defining a MIMCap;

removing portions of the resist to expose portions of the second insulating layer;

removing the exposed second insulating layer, the cap layer, and portions of the first insulating layer, leaving portions of the first conductive lines exposed;

removing the remaining resist;

depositing a capacitor dielectric over the first conductive lines;

depositing a second conductive material over the capacitor dielectric to form second conductive lines;

coupling together portions of the first conductive lines; and

coupling together portions of the second conductive lines, wherein portions of the first and second conductive lines comprise the plates of a MIMCap, the MIMCap plates having horizontal and vertical portions.

17. The method according to claim 16, further comprising, after forming the trenches within the first insulating layer:

depositing a metal liner over the first insulating layer and within the trenches; and

forming a seed layer over the metal liner.

18. The method according to claim 17, further comprising, after filling the trenches with a first conductive material:

chemically-mechanically polishing the wafer to remove the metal liner, seed layer, and first conductive material from the first insulating layer top surface.

19. The method according to claim 18 wherein depositing a metal liner comprises depositing a copper liner;

wherein forming a seed layer comprises forming a copper seed layer;

wherein filling the first insulating material trenches comprises filling the trenches with a material comprising copper; and

wherein forming the second conductive lines comprises forming tungsten lines.

20. The method according to claim 16, wherein removing the exposed first and second insulating layers and cap layer comprises a reactive ion etch (RIE) process.

21. The method according to claim 16 wherein forming the first and second insulating layers comprise forming inter-level dielectric layers.

22. The method according to claim 21, further comprising depositing a third insulating layer over the second insulating layer and the second conductive lines.