Semiconductor data storage apparatus

• US 6,627,960 B2
• Filed: 06/19/2001
• Issued: 09/30/2003
• Est. Priority Date: 08/23/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nii, Koji, Okada, Yoshinori
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US09/883,354
• Publication Number:
  US 20020024049A1
• Time in Patent Office: 833 Days
• Field of Search: 257/903, 257/904, 257/369, 257/371, 257/67, 257/393, 257/206
• US Class Current: 257/371
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. The drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. The drain of an another PMOS transistor and the gate of still another PMOS transistor are connected to the first node. The drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacitance and drain capacitance of these PMOS transistors is appended to the two nodes.

Claims

1. A semiconductor data storage apparatus comprising:

a first inverter having an input connected to a first node and an output connected to a second node;

a second inverter haying an input connected to the second node and an output connected to the first node;

a first MOS transistor having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node; and

a second MOS transistor having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, wherein

said first inverter includes a third MOS transistor of a first conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, and a fourth MOS transistor of a second conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node;

said second inverter includes a fifth MOS transistor of the first conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, and a sixth MOS transistor of the second conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node;

one of the source and drain electrodes of said second MOS transistor and one of the source and drain electrodes of the one of said third and fourth MOS transistors, which is of the same conductivity type as said second MOS transistor, share a common diffusion region, and

one of the source and drain electrodes of said first MOS transistor and one of the source and drain electrodes of one said fifth and sixth MOS transistors, which is of the same conductivity type as said first MOS transistor, share a common diffusion region.

2. The semiconductor data storage apparatus according to claim 1, further comprising at least one seventh MOS transistor having a source electrode and a drain electrode, one of the source and drain electrodes being connected to at least one of said first and second nodes, said at least one seventh MOS transistor reading stored data held at said first and second nodes and writing data to said first and second nodes.

3. A semiconductor data storage apparatus comprising:

a first inverter having an input connected to a first node and an output connected to a second node;

a second inverter having an input connected to the second node and an output connected to the first node;

a first MOS transistor having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node; and

a second MOS transistor having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, wherein

said first inverter includes a third MOS transistor of a first conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, and a fourth MOS transistor of a second conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node;

said second inverter includes a fifth MOS transistor of the first conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, and a sixth MOS transistor of the second conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node; and

said first and second MOS transistors are of the first conductivity type, and said first, second, third, and fifth MOS transistors are located in a common well region of the second conductivity type.

4. The semiconductor data storage apparatus according to claim 3, further comprising at least one seventh MOS transistor having a source electrode and a drain electrode, one of the source and drain electrodes being connected to at least one of said first and second nodes, said at least one seventh MOS transistor reading stored data held at said first and second nodes and writing data to said first and second nodes.

5. A semiconductor data storage apparatus comprising:

a first inverter having an input connected to a first node and an output connected to a second node;

a second inverter haying an input connected to the second node and an output connected to the first node;

a first MOS transistor having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node;

a second MOS transistor having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, wherein

said first inverter includes a third MOS transistor of a first conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, and a fourth MOS transistor of a second conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node; and

said second inverter includes a fifth MOS transistor of the first conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, and a sixth MOS transistor of the second conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node;

a seventh MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, the other of the source and drain electrodes being connected to a first bit line transmitting data, and having a gate electrode connected to a first word line; and

an eight MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, the other of the source and drain electrodes being connected to a second bit line transmitting data, and having a gate electrode connected to the first word line, wherein

said first and second MOS transistors are of the second conductivity type,

said first, second, fourth, and sixth MOS transistors are arranged in a first row,

said third, fifth, seventh, and eighth MOS transistors are arranged in a second row adjacent to the first row.

6. The semiconductor data storage apparatus according to claim 5, further comprising at least one ninth MOS transistor having a source electrode and a drain electrode, one of the source and drain electrodes being connected to at least one of said first and second nodes, said at least one ninth MOS transistor reading stored data held at said first and second nodes and writing data to said first and second nodes.

7. The semiconductor data storage apparatus according to claim 5, further comprising:

a ninth MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, the other of the source and drain electrodes being connected to a third bit line transmitting data, and having a gate electrode connected to a second word line;

a tenth MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, the other of the source and drain electrodes being connected to a fourth bit line transmitting data, and having a gate electrode connected to the second word line;

an eleventh MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, and having a gate electrode connected to the second node; and

a twelfth MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, and having a gate electrode connected to the first node, wherein said ninth to twelfth MOS transistors are arranged in a third row, adjacent to and on an opposite side of the first row from the second row.

8. The semiconductor data storage device according to claim 5, further comprising:

a ninth MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to a third node, the other of the source and drain electrodes being connected to a second bit line transmitting data, and having a gate electrode connected to a second word line;

a tenth MOS transistor of the first conductivity type having a source electrode and a drain electrode, one of the source and drain electrodes being connected to a third bit line transmitting data, and having a gate electrode connected to a word line which may be the second word line;

an eleventh MOS transistor of the first conductivity type having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the third node, and having gate electrode connected to the first node; and

a twelfth MOS transistor of the first conductivity type, having a source electrode and a drain electrode, one of the source and drain electrodes being connected to the fourth node, and having a gate electrode connected to the second node, wherein said ninth, tenth, and twelfth MOS transistors are arranged in a third row, adjacent to and on an opposite side of the first row from the second row.

9. A semiconductor data storage apparatus comprising:

a first inverter having an input connected to a first node and an output connected to a second node;

a second inverter having an input connected to the second node and an output connected to the first node;

a first MOS transistor having a sate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node; and

a second MOS transistor having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, wherein

said first and second MOS transistors are of the same conductivity type, and the source electrodes and drain electrodes of said first and second MOS transistors not connected to the first and second nodes share a common diffusion region.

10. The semiconductor data storage apparatus according to claim 9, further comprising at least one third MOS transistor having a source electrode and a drain electrode, one of the source and drain electrodes being connected to at least one of said first and second nodes, said at least one third MOS transistor reading stored data held at said first and second nodes and writing data to said first and second nodes.

11. The semiconductor data storage apparatus according to claim 9, further comprising:

a first contact extending from a first diffusion region and connected to the first node, the first diffusion region being the one of source and drain electrodes of said first MOS transistor connected to the first node; and

a second contact extending from a second diffusion region and connected to the second node, the second diffusion region being the one of source and drain electrodes of said second MOS transistor connected to the second node, wherein the first and second contacts extend from the first and second diffusion regions in first and second directions, but no contacts extend from the common diffusion region in the first or second directions.

12. The semiconductor data storage apparatus according to claim 9, wherein

said first inverter includes a third MOS transistor of a first conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node, and a fourth MOS transistor of a second conductivity type, having a gate electrode connected to the first node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the second node;

and

said second inverter includes a fifth MOS transistor of the first conductivity type, having a gate electrode connected to the second note and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node, and a sixth MOS transistor of the second conductivity type, having a gate electrode connected to the second node and a source electrode and a drain electrode, one of the source and drain electrodes being connected to the first node.

13. A semiconductor data storage apparatus comprising:

a first MOS transistor having a gate electrode connected to a first node, a first of a source electrode and a drain electrode receiving a fixed voltage, and a second of said source electrode and said drain electrode connected to a second node;

a second MOS transistor of the same conductivity type as said first MOS transistor, having a gate connected to the second node, a first of a source electrode and a drain electrode receiving the fixed voltage, and a second of the source electrode an the drain electrode connected to the first node;

a third MOS transistor having a gate electrode connected to the second node, a first of a source electrode and a drain electrode connected to the first node, and a second of the source electrode and the drain electrode connected to a third node; and

a fourth MOS transistor of the same conductivity type as said third MOS transistor, having a gate electrode connected to the first node, a first of a source electrode and a drain electrode connected to the second node, and a second of the source electrode and the drain electrode connected to the third node, wherein only said second of the source electrodes and the drain electrodes of said third and fourth MOS transistors are connected to said third node, wherein the second of the source electrodes and the drain electrodes of said third and fourth MOS transistors share a common diffusion region.

14. The semiconductor data storage apparatus according to claim 13, further comprising:

a fifth MOS transistor having a gate electrode connected to a word line, and a source electrode and a drain electrode, one of the source and drain electrodes being connected to a first bit line, the other of the source and drain electrodes being connected to the first node, and

a sixth MOS transistor having a gate electrode connected to the word line, and a source electrode and a drain electrode, one of the source and drain electrodes being connected to a second bit line, the other of the source and drain electrodes being connected to the second node.

15. The semiconductor data storage apparatus according to claim 13, further comprising:

a first contact extending from a first diffusion region and connected to the first node, the first diffusion region being the one of source and drain electrodes of said first MOS transistor connected to the first node; and

a second contact extending from a second diffusion region and connected to the second node, the second diffusion region being the one of source and drain electrodes of said second MOS transistor connected to the second node, wherein the first and second contacts extend from the first and second diffusion regions in first and second directions, but no contacts extend from common diffusion region in the first or second directions.