Fully connected cache coherent multiprocessing systems

  • US 6,633,945 B1
  • Filed: 07/08/1999
  • Issued: 10/14/2003
  • Est. Priority Date: 12/07/1997
  • Status: Expired due to Term
First Claim
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1. A multi-processor shared memory system comprising:

  • a first set of point-to-point connections;

    a first set of processors each coupled to one of the first set of point-to-point connections;

    a first memory coupled to one of the first set of point-to-point connections;

    a first flow control unit including a first data switch coupled to the first set of point-to-point connections wherein the first data switch is configured to interconnect the first set of point-to-point connections to provide first data paths between the first memory and the first set of processors;

    a second set of point-to-point connections;

    a second set of processors each coupled to one of the second set of point-to-point connections;

    a second memory coupled to one of the second set of point-to-point connections;

    a second flow control unit including a second data switch coupled to the second set of point-to-point connections wherein the second data switch is configured to interconnect the second set of point-to-point connections to provide second data paths between the second memory and the second set of processors; and

    a third point-to-point connection coupled to the first data switch and to the second data switch wherein the first data switch is configured to interconnect the first set of point-to-point connections to the third point-to-point connection and the second data switch is configured to interconnect the second set of point-to-point connections to the third point-to-point connection to provide third data paths between the second memory and the first set of processors and between the first memory and the second set of processors.

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