Semiconductor memory with refresh and method for operating the semiconductor memory
First Claim
Patent Images
1. A semiconductor memory, comprising:
- at least one memory cell;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal; and
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier.
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Abstract
To carry out a refresh operation, a semiconductor memory having dynamic memory cells includes a sense amplifier that, on the output side, provides a signal depending on a control of a bit line driver. The bit line driver is embodied as an adiabatic amplifier, preferably, having current paths through which charges that are to be exchanged during a charge-reversal operation are buffer-stored in capacitors. Power loss for the charge reversal of the bit line capacitances is thereby saved. A method for operating the memory is also provided.
24 Citations
15 Claims
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1. A semiconductor memory, comprising:
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at least one memory cell;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal; and
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
said adiabatic amplifier has first and second output terminals;
a further bit line is connected to said sense amplifier; and
said first and second output terminals of said adiabatic amplifier are respectively connected to said bit line and said further bit line.
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3. The semiconductor memory according to claim 2, wherein:
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said adiabatic amplifier has at least three current paths connected between said bit line and said further bit line;
each of said current paths has a series circuit of controlled paths of two transistors with a coupling node;
said coupling node of said transistors for two of said current paths is connected to a respective terminal for a supply potential; and
a capacitive element is connected to said coupling node of said transistors for another of said current paths.
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4. The semiconductor memory according to claim 3, wherein:
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said transistors have control terminals; and
a control device has an output side connected to said control terminals of said transistors to control an adiabatic amplification operation of complementary signals on said bit lines dependent upon the output signal of said sense amplifier.
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5. The semiconductor memory according to claim 3, including:
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further capacitive elements; and
at least two further current paths connected between said first and second output terminals, each of said further current paths having two transistors with a coupling node, said two transistors connected in series by controlled paths, said coupling node connected to a respective one of said further capacitive elements.
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6. The semiconductor memory according to claim 4, including:
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further capacitive elements; and
at least two further current paths connected between said first and second output terminals, each of said further current paths having two transistors with a coupling node, said two transistors connected in series by controlled paths, said coupling node connected to a respective one of said further capacitive elements.
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7. The semiconductor memory according to claim 4, wherein:
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said control device has a read-only memory and a counter connected to and driving said read-only memory; and
said read-only memory has an output side connected to said control terminals of said transistors.
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8. The semiconductor memory according to claim 1, wherein:
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said sense amplifier is a plurality of sense amplifiers;
a plurality of bit line pairs are respectively connected to one of said sense amplifiers;
said adiabatic amplifier is a single adiabatic amplifier with an input side and an output side;
said input side of said single adiabatic amplifier is connected to said sense amplifiers;
said single adiabatic amplifier is driven by each of said sense amplifiers;
at least one controllable switching device is connected to said output side of said single adiabatic amplifier;
said switching device is connected to bit lines of said bit line pairs for connecting said output side of said single adiabatic amplifier to said bit lines of said bit line pairs; and
said switching device is programmed to drive a respective one of said bit line pairs based upon the output signal from a respective one of said sense amplifiers connected to said one of said bit line pairs and fed to said single adiabatic amplifier by said single adiabatic amplifier through said switching device.
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9. The semiconductor memory according to claim 1, wherein:
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said sense amplifier is a plurality of sense amplifiers;
a plurality of bit line pairs are respectively connected to one of said sense amplifiers;
said adiabatic amplifier is a single adiabatic amplifier with an input side and an output side;
said input side of said single adiabatic amplifier is connected to said sense amplifiers;
said single adiabatic amplifier is driven by each of said sense amplifiers;
at least one controllable switching device is connected to said output side of said single adiabatic amplifier;
said switching device is connected to bit lines of said bit line pairs for connecting said output side of said single adiabatic amplifier to said bit lines of said bit line pairs; and
for an output signal directly sent to said single adiabatic amplifier from one of said sense amplifiers connected to a respective one of said bit line pairs, said switching device is programmed to drive said one of said bit line pairs with said single adiabatic amplifier through said switching device.
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10. The semiconductor memory according to claim 1, wherein:
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said memory cell has a selection transistor and a storage capacitor; and
said adiabatic amplifier refreshes a charge content of said storage capacitor.
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11. A two-mode semiconductor memory, comprising:
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at least one memory cell having a selection transistor and a storage capacitor;
a bit line connected to said memory cell;
a sense amplifier having an output, said sense amplifier;
connected to said bit line;
amplifying a signal read from said memory cell; and
generating, at said output, an output signal derived from the signal;
an adiabatic amplifier connected to said bit line and to said output and driven by the output signal of said sense amplifier to write back the signal read from said memory cell to said memory cell in amplified form dependent upon the output signal of said sense amplifier;
said adiabatic amplifier refreshing a charge content of said storage capacitor; and
a first operating mode carrying out a reading or writing access of a data value at said memory cell with a relatively high power loss consumption and a second operating mode refreshing the data value stored in said memory cell through said adiabatic amplifier with a relatively lower power loss consumption. - View Dependent Claims (12)
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13. A method for operating a semiconductor memory, which comprises:
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providing a two-mode semiconductor memory having;
at least one memory cell;
a bit line connected to the memory cell;
a sense amplifier having an output, the sense amplifier connected to the bit line; and
an adiabatic amplifier connected to the bit line and to the output of the sense amplifier;
generating an output signal derived from the signal at the output of the sense amplifier;
in a first operating mode, amplifying a signal read from the memory cell with the sense amplifier and providing the signal at an external output terminal of the semiconductor memory; and
in a second operating mode, feeding the output signal of the sense amplifier to the adiabatic sense amplifier to control, dependent upon the output signal of the sense amplifier, the adiabatic sense amplifier such that the signal read from the memory cell is written back to the memory cell again after adiabatic amplification. - View Dependent Claims (14, 15)
carrying out the first operating mode as a normal operating mode of the memory; and
carrying out the second operating mode as a power-saving mode of the memory, the power-saving mode having a relatively lower power loss compared to a power loss of the normal operating mode.
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15. The method according to claim 13, wherein:
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the first operating mode is a normal operating mode of the memory; and
the second operating mode is a power-saving mode of the memory having a relatively lower power loss compared to a power loss of the normal operating mode.
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Specification