Silicide MOSFET architecture and method of manufacture

• US 6,642,119 B1
• Filed: 08/08/2002
• Issued: 11/04/2003
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sinha, Shankar, Pelella, Mario M., Chan, Simon S.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US10/215,171
• Time in Patent Office: 453 Days
• Field of Search: 438/151, 438/197, 438/231, 438/303, 438/306, 438/311, 438/366, 438/533, 438/514, 438/542, 438/559, 438/560, 438/595, 438/630, 438/652, 438/656, 438/682, 438/952
• US Class Current: 438/303
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 438/952 Utilizing antireflective layer

Abstract

The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Claims

1. A method of forming a transistor, comprising:

forming a gate structure having lateral edges associated therewith over a semiconductor substrate by patterning a gate material using a mask structure overlying a top portion thereof;

forming first sidewall spacers on the lateral edges of the gate structure;

forming extension regions in the semiconductor substrate that are self-aligned with respect to the gate structure;

forming a first silicide on the extension regions, wherein the first silicide does not form on the gate structure due to the mask structure residing thereon;

forming second sidewall spacers on the lateral edges of the gate structure and covering the first sidewall spacers;

forming a source region and a drain region under the extension regions, respectively, the source and drain regions being formed via implantation through the first silicide on the extension regions; and

forming a second silicide on the first silicide and on a top portion of the gate structure after forming the source and drain regions.

2. The method of claim 1, further comprising removing the mask structure prior to forming the second silicide on the top portion of the gate structure.

3. The method of claim 2, wherein the mask structure is removed prior to forming the source and drain regions via implantation, wherein the implantation also dopes the gate structure.

4. The method of claim 1, wherein the first sidewall spacers are formed before the formation of the extension regions.

5. The method of claim 1, wherein forming the first silicide comprises:

depositing one of a titanium and a tungsten layer over the semiconductor substrate having the gate structure and first sidewall spacers; and

performing thermal processing, wherein the titanium or tungsten reacts with the source and drain regions to form a titanium silicide or a tungsten silicide thereat, respectively.

6. The method of claim 1, wherein forming the second silicide comprises:

depositing a metal layer over the semiconductor substrate having the gate structure and first and second spacers thereon; and

performing thermal processing, wherein the metal reacts with the first suicide over the extension regions in regions not covered by the second spacers and on the top portion of the gate structure.

7. The method of claim 6, wherein the second silicide comprises, tungsten silicide.

8. The method of claim 1, further comprising forming an insulating layer in the semiconductor substrate, thereby defining a bottom portion of the semiconductor substrate below the insulating layer, and a top portion of the semiconductor substrate thereabove, and wherein the extension regions and source and drain regions are formed in the top portion of the semiconductor substrate, thereby forming a silicon-over-insulator (SOI) transistor.

9. A method of forming a transistor, comprising:

forming a gate structure having lateral edges associated therewith over a semiconductor substrate by patterning a gate material using a mask structure overlying a top portion thereof;

forming first sidewall spacers on the lateral edges of the gate structure;

forming source and drain regions in the semiconductor substrate that are self-aligned with respect to the gate structure with an extension region implant;

forming a first silicide on the source and drain regions, wherein the first silicide does not form on the gate structure due to the mask structure residing thereon;

forming second sidewall spacers on the lateral edges of the gate structure and covering the first sidewall spacers; and

forming a second silicide on the first silicide and on a top portion of the gate structure after forming the source and drain regions.

10. The method of claim 9, further comprising removing the mask structure prior to forming the second silicide on the top portion of the gate structure.

11. The method of claim 10, wherein the mask structure is removed prior to forming the source and drain regions via the extension region implant, wherein the implantation also dopes the gate structure.

12. The method of claim 9, wherein the first sidewall spacers are formed before the formation of the source and drain regions.

13. The method of claim 9, wherein forming the first silicide comprises:

depositing one of a titanium and a tungsten layer over the semiconductor substrate having the gate structure and first sidewall spacers; and

performing thermal processing, wherein the titanium or tungsten reacts with the source and drain regions to form a titanium silicide or a tungsten silicide thereat, respectively.

14. The method of claim 9, wherein forming the second silicide comprises:

depositing a metal layer over the semiconductor substrate having the gate structure and first and second spacers thereon; and

performing thermal processing, wherein the metal reacts with the first silicide over the source and drain regions in regions not covered by the second spacers and on the top portion of the gate structure.

15. The method of claim 14, wherein the second silicide comprises tungsten silicide.

16. The method of claim 9, further comprising forming an insulating layer in the semiconductor substrate, thereby defining a bottom portion of the semiconductor substrate below the insulating layer, and a top portion of the semiconductor substrate thereabove, and wherein the extension regions and source and drain regions are formed in the top portion of the semiconductor substrate, thereby forming a silicon-over-insulator (SOI) transistor.