Grounded body SOI SRAM cell

• US 6,646,305 B2
• Filed: 07/25/2001
• Issued: 11/11/2003
• Est. Priority Date: 07/25/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Bryant, Andres, Rankin, Jed H., Gauthier, Robert J. Jr., Mann, Randy W., Assaderaghi, Fariborz, Cottrell, Peter E.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/915,061
• Publication Number:
  US 20030020116A1
• Time in Patent Office: 839 Days
• Field of Search: 251/347-354
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to V_DD.

Claims

1. A semiconductor memory device comprising:

an SOI substrate having a thin silicon layer on top of a buried insulator;

an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in said thin silicon layer, each said I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region; and

a first connecting region in said thin silicon layer abutting the source and body regions of each said I/O NFETS, said first connecting region electrically connected to ground.

2. The semiconductor memory device of claim 1, wherein said first connecting region abuts the body regions of said latch NFETs.

3. The semiconductor memory device of claim 2, further comprising a second connecting region in said thin silicon layer, abutting the body regions of said latch PFETs, said second connecting region electrically connected to V_DD.

4. The semiconductor memory device of claim 2 wherein said first connecting region abuts the source region of each said latch NFET.

5. The semiconductor memory device of claim 3 wherein said first connecting region abuts the source region of each said latch NFET and said second connecting region abuts the source region of each said latch PFET.

6. A semiconductor memory device comprising:

an SOI substrate having a thin silicon layer on top of a buried insulator;

an SRAM comprising two I/O NFETs, two latch NFETs and two latch PFETs located in said thin silicon layer, each said I/O NFET, latch NFET and latch PFET having a body region between a source region and a drain region;

a first connecting region in said thin silicon layer, said first connecting region electrically connected to ground; and

a pair of second connecting regions in said thin silicon layer, each second connecting region co-extensive with one of said body regions of said I/O NFETs and between said body regions and said first connecting region.

7. The semiconductor memory device of claim 6 further comprising a pair of third connecting regions in said thin silicon layer, each third connecting region co-extensive with one of said body regions of said latch NFETs and between said body regions and said first connecting region.

8. The semiconductor memory device of claim 7 further comprising a pair of fifth connecting regions in said thin silicon layer, each fifth connecting region co-extensive with one of said body regions of said latch PFETs and between said body regions and a sixth connecting region, said sixth connecting region electrically connected to V_DD.

9. The semiconductor memory device of claim 8 wherein said first connecting region abuts the source region of each said I/O NFET and the source region of each said latch NFET and said sixth connecting region abuts the source region of each said latch PFET.

10. The semiconductor memory device of claim 7 wherein said first connecting region abuts the source region of each said I/O NFET and the source region of each said latch NFET.

11. The semiconductor memory device of claim 6 wherein said first connecting region abuts the source region of each said I/O NFET.