Multiprocessor computer systems with command FIFO buffer at each target device

CAFC
  • US 6,647,450 B1
  • Filed: 10/06/2000
  • Issued: 11/11/2003
  • Est. Priority Date: 10/06/1999
  • Status: Expired due to Term
First Claim
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1. A multiprocessor computer system comprising:

  • a) a split transaction global bus;

    b) at least one target device connected to the split transaction global bus, the at least one target device having a command FIFO buffer for storing a command issued by the split transaction global bus to the target device such that the at least one target device may accept the issued command both while it is executing a previously-issued command and while it is not executing any command; and

    c) a plurality of master devices connected to the split transaction global bus and having means for releasing the split transaction global bus for use by another device connected to the split transaction global bus after receiving an acknowledgment of command receipt from the at least one target device.

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