Method and apparatus for providing power based on the amount of data stored in buffers

• US 6,647,502 B1
• Filed: 07/13/1999
• Issued: 11/11/2003
• Est. Priority Date: 07/13/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ohmori, Mutsuhiro
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/352,384
• Time in Patent Office: 1,582 Days
• Field of Search: 713/300-340, 713/600-601, 710/52-61
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power supply controlling circuit by which further reduction of power consumption in a circuit can be achieved includes a clock controller. The clock controller detects a processing state of a module based on an amount of data stored in a FIFO memory. For example, when the load to the module is not very high, the clock controller continuously lowers the frequency of a system clock signal to be supplied to the module and continuously lowers the power supply voltage to the module.

Claims

1. A power consumption controlling circuit for controlling (1) a power consumption of a first module which performs predetermined processing in synchronism with a first clock signal and (2) a power consumption of a second module which performs predetermined processing in synchronism with a second clock signal, comprising:

a first storage unit in a stage preceding said first module, said first storage unit for storing data to be processed by said first module and reading data out in accordance with the first clock signal;

first detection means for detecting a processing state of said first module based on an amount of data stored in said first storage unit;

first control means for varying the frequency of the first clock signal and/or a first power voltage supplied to said first module in response to a result of the detection of said detection means;

a second storage unit in a stage preceding said second module, said second storage unit for storing data to be processed by said second module in accordance with the first clock signal and reading data out in accordance with the second clock signal;

second detection means for detecting a processing state of said second module based on an amount of data stored in said second storage unit; and

second control means for varying the frequency of the second clock signal and/or a second power voltage supplied to said second module in response to a result of the detection of said detection means.

2. The power consumption controlling circuit according to claim 1, wherein, when the first power voltage is to be lowered, said first control means first lowers the frequency of the first clock signal and then varies the first power voltage, but when the frequency of the first clock signal is to be raised, said first control means first raises the first power voltage and then varies the frequency of the first clock signal.

3. The power consumption controlling circuit according to claim 1, wherein said first detection means includes counting means for incrementing or decrementing a count value thereof in response to an amount of data stored in said first storage unit and detects the processing state of said first module based on the count value of said counting means.

4. The power consumption controlling circuit according to claim 3, further comprising a phase locked loop circuit which operates in synchronism with the first clock signal, said control means varying a dividing ratio of said PLL circuit in accordance with the count value of said counting means to vary the frequency of the first clock signal.

6. The power consumption controlling circuit according to claim 1, wherein, when the second power voltage is to be lowered, said second control means second lowers the frequency of the second clock signal and then varies the second power voltage, but when the frequency of the second clock signal is to be raised, said second control means second raises the second power voltage and then varies the frequency of the second clock signal.

7. The power consumption controlling circuit according to claim 1, wherein said second detection means includes counting means for incrementing or decrementing a count value thereof in response to an amount of data stored in said second storage unit and detects the processing state of said second module based on the count value of said counting means.

8. The power consumption controlling circuit according to claim 7, further comprising a phase locked loop circuit which operates in synchronism with the second clock signal, said control means varying a dividing ratio of said PLL circuit in accordance with the count value of said counting means to vary the frequency of the second clock signal.

9. A power consumption controlling circuit according to claim 1, wherein both of said first and second clock signals are derived from a system clock.

5. A power consumption controlling method for controlling (1) a power consumption of a first module which performs predetermined processing in synchronism with a first clock signal, and (2) a power consumption of a second module which performs predetermined processing in synchronization with a second clock signal comprising the steps of:

storing data to be processed by said first module in a first storage unit preceding said first module;

reading data out of said first storage unit in accordance with the first clock signal;

detecting a processing state of said first module based on an amount of data stored in said first storage unit;

varying the frequency of the first clock signal and/or a first power voltage supplied to said first module in response to a result of the detection of the processing state of said first module;

storing data to be processed by said second module in a second storage unit in accordance with the first clock signal, said second storage unit preceding said second module;

reading data out of said second storage unit in accordance with the second clock signal;

detecting a processing state of said second module based on an amount of data stored in said second storage unit; and

varying the frequency of the second clock signal and/or a second power voltage supplied to said second module in response to a result of the detection of the processing state of said second module.