Method and apparatus for providing power based on the amount of data stored in buffers
First Claim
1. A power consumption controlling circuit for controlling (1) a power consumption of a first module which performs predetermined processing in synchronism with a first clock signal and (2) a power consumption of a second module which performs predetermined processing in synchronism with a second clock signal, comprising:
- a first storage unit in a stage preceding said first module, said first storage unit for storing data to be processed by said first module and reading data out in accordance with the first clock signal;
first detection means for detecting a processing state of said first module based on an amount of data stored in said first storage unit;
first control means for varying the frequency of the first clock signal and/or a first power voltage supplied to said first module in response to a result of the detection of said detection means;
a second storage unit in a stage preceding said second module, said second storage unit for storing data to be processed by said second module in accordance with the first clock signal and reading data out in accordance with the second clock signal;
second detection means for detecting a processing state of said second module based on an amount of data stored in said second storage unit; and
second control means for varying the frequency of the second clock signal and/or a second power voltage supplied to said second module in response to a result of the detection of said detection means.
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Abstract
A power supply controlling circuit by which further reduction of power consumption in a circuit can be achieved includes a clock controller. The clock controller detects a processing state of a module based on an amount of data stored in a FIFO memory. For example, when the load to the module is not very high, the clock controller continuously lowers the frequency of a system clock signal to be supplied to the module and continuously lowers the power supply voltage to the module.
95 Citations
9 Claims
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1. A power consumption controlling circuit for controlling (1) a power consumption of a first module which performs predetermined processing in synchronism with a first clock signal and (2) a power consumption of a second module which performs predetermined processing in synchronism with a second clock signal, comprising:
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a first storage unit in a stage preceding said first module, said first storage unit for storing data to be processed by said first module and reading data out in accordance with the first clock signal;
first detection means for detecting a processing state of said first module based on an amount of data stored in said first storage unit;
first control means for varying the frequency of the first clock signal and/or a first power voltage supplied to said first module in response to a result of the detection of said detection means;
a second storage unit in a stage preceding said second module, said second storage unit for storing data to be processed by said second module in accordance with the first clock signal and reading data out in accordance with the second clock signal;
second detection means for detecting a processing state of said second module based on an amount of data stored in said second storage unit; and
second control means for varying the frequency of the second clock signal and/or a second power voltage supplied to said second module in response to a result of the detection of said detection means. - View Dependent Claims (2, 3, 4, 6, 7, 8, 9)
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5. A power consumption controlling method for controlling (1) a power consumption of a first module which performs predetermined processing in synchronism with a first clock signal, and (2) a power consumption of a second module which performs predetermined processing in synchronization with a second clock signal comprising the steps of:
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storing data to be processed by said first module in a first storage unit preceding said first module;
reading data out of said first storage unit in accordance with the first clock signal;
detecting a processing state of said first module based on an amount of data stored in said first storage unit;
varying the frequency of the first clock signal and/or a first power voltage supplied to said first module in response to a result of the detection of the processing state of said first module;
storing data to be processed by said second module in a second storage unit in accordance with the first clock signal, said second storage unit preceding said second module;
reading data out of said second storage unit in accordance with the second clock signal;
detecting a processing state of said second module based on an amount of data stored in said second storage unit; and
varying the frequency of the second clock signal and/or a second power voltage supplied to said second module in response to a result of the detection of the processing state of said second module.
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Specification