Compact analog-multiplexed global sense amplifier for rams

• US 6,650,572 B2
• Filed: 08/21/2002
• Issued: 11/18/2003
• Est. Priority Date: 07/12/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Issa, Sami
• Primary Examiner(s): Lam, David
• Application Number:
  US10/224,841
• Publication Number:
  US 20030021159A1
• Time in Patent Office: 454 Days
• Field of Search: 365/189.02, 365/205, 365/190, 365/189.01, 365/207, 365/230.03, 365/230.04
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers).

In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. The global bit line pairs with no voltage development generate zero voltage development on the local bit lines and the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

Claims

1. A RAM having a plurality of local bit lines and a plurality of global bit lines comprising:

means for coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines;

means for selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines for a write operation; and

means for coupling non-selected global bit lines to a vdd signal during the write operation.

2. The RAM of claim 1, wherein the means for coupling a local bit line to a respective global bit line comprises of a MOS transistor.

3. The RAM of claim 1, further comprising means for sensing a respective data cell and writing data to the respective data cell during the write operation.

4. The RAM of claim 1, further comprising means for limiting voltage swing development on each of the plurality of global bit lines.

5. The RAM of claim 1, further comprising means for refreshing data cells corresponding to non-selected global bit lines during the write operation.

6. The RAM of claim 1, wherein the plurality of global bit lines comprises eight global bit lines.

7. The RAM of claim 1, wherein the plurality of global bit lines comprises sixteen global bit lines.

8. The RAM of claim 1, wherein the plurality of global bit lines comprises thirty two global bit lines.

9. A method for writing data to a RAM having a plurality of local bit lines and a plurality of global bit lines comprising:

coupling a local bit line of the plurality of local bit lines to a respective global bit line of the plurality of global bit lines;

selecting a local bit line of the plurality of local bit lines and a respective global bit line of the plurality of global bit lines during the writing data; and

coupling non-selected global bit lines to a vdd signal during the writing data.

10. The method of claim 9, further comprising sensing a respective data cell and writing the data to the respective data cell.

11. The method of claim 9, further comprising limiting voltage swing development on each of the plurality of global bit lines.

12. The method of claim 9, further comprising refreshing data cells corresponding to non-selected global bit lines.

13. A RAM with differential local sensing means comprising:

an odd block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective odd bit line;

an even block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective even bit line; and

a plurality of local sense amplifiers positioned between the odd block of data cells and the even block of data cells,

wherein each local sense amplifier of the plurality of local sense amplifiers is shared by a respective odd bit line, a respective even bit line, and a respective global bit line, and comprises of;

four transistors configured as two cross-coupled latches having a first output and a second output;

a first gate transistor for coupling the first output of the two cross-coupled latches to the respective global bit line; and

a second gate transistor for coupling the second output of the two cross-coupled latches to a complement signal of the respective global bit line.

14. The RAM of claim 13, wherein the each local sense amplifier of the plurality of local sense amplifiers further comprises a current sink transistor coupled between the two cross-coupled latches and a ground signal.

15. The RAM of claim 13, wherein the first gate transistor and the second gate transistor are configured to limit voltage swing on the respective global bit line for read and write cycles.

16. The RAM of claim 13, wherein the first gate transistor and the second gate transistor are NMOS transistors.

17. The RAM of claim 13, wherein the two cross-coupled latches comprise of two NMOS transistors and two PMOS transistors.