Correlator co-processor for CDMA RAKE receiver operations

• US 6,650,694 B1
• Filed: 06/30/2000
• Issued: 11/18/2003
• Est. Priority Date: 02/18/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lee, Kang, Honore, Francis, Sriram, Sundararajan, Brown, Katherine G.
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US09/607,410
• Time in Patent Office: 1,236 Days
• Field of Search: 375/130, 375/142, 375/145, 375/147, 375/149, 375/150, 370/208, 370/209, 370/342, 370/335
• US Class Current: 375/150
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/70752 Partial correlation
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 2001/70706 using a code tracking loop, e.g. a delay locked loop
• CPC Class Codes: H04B 2201/70711 with modular structure

Abstract

A programmable, flexible, vector correlation engine for CDMA mobile and base station chip rate signal processing. A correlator co-processor (CCP) performs the de-spreading tasks for a RAKE receiver, early/late correlations for time tracking, and has provision for coherent accumulation of different lengths. The CCP also performs energy estimation and non-coherent accumulation functions. The CCP can also perform correlation functions required for delay profile estimation, and for search/acquisition functions. The same centralized Data Path is used to perform all these functions; a common controller generates signals into the Data Path in response to tasks initiated by a host processor (e.g., DSP). The tasks written into the CCP are performed effectively in parallel by the CCP Data Path.

Claims

1. A correlator co-processor (CCP) for a wireless communication system comprising:

a pseudo-noise (PN) code generator for generating PN codes;

a Walsh code generator for generating Walsh codes;

at least one input buffer configured to receive and store in-phase and quadrature phase (I/Q) sub-chip samples;

at least one chip counter (GCC) configured to count chip samples received by the at least one input buffer and count modulo a WCDMA long code length and further configured as a local timing reference for the CCP;

a data path configured to receive and process samples of the PN codes, samples of the Walsh codes and the I/Q sub-chip samples;

at least one task buffer configured to store a list of programmably executable tasks;

at least one configuration table buffer in communication with the at least one task buffer and configured to store a plurality of configuration tables that specify how each task within the list of programmably executable tasks is implemented;

an interrupt generator;

at least one output data buffer; and

a controller in communication with the data path, the at least one task buffer, the at least one configuration table, the interrupt generator, the PN code generator, the Walsh code generator, the GCC and the at least one output buffer, such that the controller, synchronized with timing signals received from the GCC and directed by the programmably executable tasks, can direct the Walsh code generator to generate the Walsh codes, can direct the PN code generator to generate the PN codes and can direct the data path to process the samples of the PN codes, the samples of the Walsh codes and the I/Q sub-chip samples and therefrom selectively generate RAKE receiver data or search results, store the RAKE receiver data or search results in the at least one output data buffer, and cause the interrupt generator to generate at least one task-based interrupt signal.

2. The correlator co-processor (CCP) according to claim 1 wherein the data path comprises a plurality of multipliers configured to multiply the I/Q samples from the at least one input buffer with samples of the PN codes and samples of the Walsh codes.

3. The correlator co-processor (CCP) according to claim 2 wherein the data path further comprises a plurality of adder trees configured to generate partial correlation data associated with the I/Q samples.

4. The correlator co-processor (CCP) according to claim 3 wherein the data path further comprises at least one coherent accumulator configured to sum the partial correlation data with data associated with at least one previous partial correlation associated with the I/Q samples.

5. The correlator co-processor (CCP) according to claim 4 wherein the data path further comprises a post-processing element configured to generate energy data and execute non-coherent accumulations associated with the I/Q chip samples.

6. The correlator co-processor (CCP) according to claim 5 wherein the data path further comprises temporary memory elements configured to store at least some of the partial correlation data, energy data and intermediate accumulation data associated with the non-coherent accumulations.

7. The correlator co-processor (CCP) according to claim 6 wherein the data path further comprises a plurality of pipeline stages configured to maximize processing capability.

8. The correlator co-processor (CCP) according to claim 1 wherein at least one output data buffer comprises at least one buffer selected from the group consisting of primary search code (PSC), delay profile estimation (DPE), long code identifier (LCI), secondary search code (SSC), Finger Max, early-ontime-late (EOL), and Finger Symbol buffers.

9. The correlator co-processor (CCP) according to claim 8 further comprising a Finger Symbol buffer (FSB) external bus capable of providing an external host processor access to FSB data.

10. The correlator co-processor (CCP) according to claim 1 wherein the controller, directed by the programmably executable tasks, is configured to further cause the interrupt generator to generate system interrupts to indicate global CCP events and error interrupts to indicate detection of error conditions.

11. The correlator co-processor (CCP) according to claim 1 further comprising an external system interface bus capable of providing an external host processor access to the at least one configuration table buffer, the interrupt generator and the at least one output data buffer.

12. The correlator co-processor (CCP) according to claim 11 wherein the external system interface bus is a RHEA bus.

13. The correlator co-processor (CCP) according to claim 11 wherein the external system interface bus in a EMIF bus.

14. A correlator co-processor (CCP) for a RAKE receiver comprising:

means for generating pseudo-noise (PN) codes;

means for generating Walsh codes;

means for receiving and storing in-phase and quadrature (I/Q) sub-chip samples;

timing means for counting chip samples received by the receiving and storing means;

data processing means for processing samples of the PN codes, samples of the Walsh codes and the I/Q sub-chip samples;

means for storing a plurality of programmably executable tasks;

means for storing a plurality of configuration tables;

means for generating interrupt signals;

means for storing output data; and

controlling means in communication with the data processing means, task storing means, configuration table storing means, interrupt generating means, PN code generating means, Walsh code generating means, timing means and output data storing means, such that the controlling means, directed by the programmably executable tasks, can direct the data processing means to process the samples of the PN codes, the samples of the Walsh codes and the I/Q sub-chip samples, and therefrom generate RAKE receiver data.

15. The correlator co-processor (CCP) according to claim 14 wherein the controlling means, directed by the programmably executable tasks can further cause the interrupt generating means to generate at least one task-based interrupt signal.

16. The correlator co-processor (CCP) according to claim 14 wherein the data processing means comprises multiplying means for multiplying the I/Q samples associated with the receiving and storing means with samples of the PN codes and samples of the Walsh codes.

21. The correlator co-processor (CCP) according to claim 14 wherein the means for storing output data comprises at least one buffer selected from the group consisting of primary search code (PSC), delay profile estimation (DPE), long code identifier (LCI), secondary search code (SSC), Finger Max, early-ontime-late (EOL), and Finger Symbol buffers.

22. The correlator co-processor (CCP) according to claim 21 further comprising means for providing a host processor direct access to data stored in the Finger Symbol buffer (FSB).

23. The correlator co-processor (CCP) according to claim 14 wherein the controlling means, directed by the programmably executable tasks, is configured to further cause the means for generating interrupt signals to generate system interrupts indicative of global CCP events and to generate error interrupts indicative of error conditions.

24. The correlator co-processor (CCP) according to claim 14 further comprising means for interfacing the CCP with RHEA bus compatible digital signal processors.

25. The correlator co-processor (CCP) according to claim 14 further comprising means for interfacing the CCP with EMIF bus compatible digital signal processors.

17. The correlator co-processor (CCP) according to 16 wherein the data processing means further comprises adding means for generating partial correlation data associated with the I/Q samples.

18. The correlator co-processor (CCP) according to claim 17 wherein the data processing means further comprises coherent accumulating means for summing the partial correlation data with data associated with at least one previous partial correlation.

19. The correlator co-processor (CCP) according to claim 18 wherein the data processing means further comprises post-processing means for generating energy data and executing non-coherent accumulations associated with the I/Q sub-chip samples.

20. The correlator co-processor (CCP) according to claim 19 wherein the data processing means further comprises temporary storing means for storing at least some of the partial correlation data, energy data and non-coherent accumulation data.

26. A correlator co-processor (CCP) for a RAKE receiver comprising:

a pseudo-noise (PN) code generator having a control input and a PN code output;

a Walsh code generator having a control input and a Walsh code output;

at least one input buffer, each input buffer having at least one in-phase and quadrature (I/Q) signal sample input, a control input, and a complex signal output;

at least one chip counter (GCC), each GCC having a signal sample input in communication with the at least one I/Q signal sample input and further having a local reference clock output;

a data path having at least one output, a first data path input in communication with the PN code output and the Walsh code output, a second data path input in communication with the complex signal output, and further having a third data path input;

at least one task buffer having an input and an output and configured to store a list of programmably executable tasks;

at least one configuration table buffer having a first output and a second output, the first output in communication with the at least one task buffer input, and further having at least one input in communication with an external system interface bus;

an interrupt generator having an input, a first output and a second output, the second output in communication with the external system interface bus;

at least one output data buffer having at least one input in communication with the at least one data path output, and further having at least one output in communication with the external system interface bus; and

a controller synchronized with the local reference clock output and having a first output in communication with the third data path input, a second output in communication with the PN code generator control input, the Walsh code generator control input and the input buffer control input, a third output in communication with the interrupt generator input, a first input in communication with the at least one task buffer output, and a second input in communication with the at least one configuration table second output.

27. The correlator co-processor (CCP) according to claim 26 wherein at least one output data buffer is a finger symbol buffer.

28. The correlator co-processor (CCP) according to claim 27 wherein the finger symbol buffer comprises an external communication bus interface output.

29. The correlator co-processor (CCP) according to claim 26 wherein the at least one output data buffer comprises at least one buffer selected from the group consisting of primary search code (PSC), delay profile estimation (DPE), long code identifier (LCI), secondary search code (SSC), finger max, early-ontime-late (EOL), and finger symbol buffers.

30. The correlator co-processor (CCP) according to claim 26 wherein the data path comprises a plurality of multipliers, a plurality of adder trees, at least one coherent accumulator, a post-processing element, and temporary data storage elements such that the data path can perform predetermined functions for a RAKE receiver.

31. The correlator co-processor (CCP) according to claim 30 wherein the predetermined functions are selected from the group consisting of de-spreading tasks, early/late correlations for time tracking, coherent accumulation of different lengths, energy estimation, non-coherent accumulation, correlations for delay profile estimation, and correlations for search/acquisition functions.

32. The correlator co-processor (CCP) according to claim 26 wherein the external system interface bus is a RHEA communication system bus.

33. The correlator co-processor (CCP) according to claim 26 wherein the external system interface bus is a EMIF communication system bus.