Conductor strip arrangement for a molded electronic component and process for molding

• US 6,653,564 B2
• Filed: 11/20/2001
• Issued: 11/25/2003
• Est. Priority Date: 11/25/2000
• Status: Active Grant

• Current Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Inventors: Scheidle, Helmut
• Primary Examiner(s): Reichard, Dean A.
• Assistant Examiner(s): OLIVA, CARMELO B
• Application Number:
  US09/991,348
• Publication Number:
  US 20020062976A1
• Time in Patent Office: 735 Days
• Field of Search: 174/52.2, 174/52.3, 174/52.4, 257/666, 257/667, 257/669, 257/692, 257/693, 257/734, 257/773, 257/787, 257/788
• US Class Current: 174/527
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

At least one semiconductor element is located on an electrically conducting conductor strip. Around the conductor strip and the at least one semiconductor element, a housing made of a molding material is arranged such that there are still frame sections of the conductor strip outside the housing. An enlarged frame section of the conductor strip is widened so as to extend into contact with, e.g. directly adjacent to or even protruding into the housing, in order to prevent the formation of a molding flash ridge on this housing surface. The enlarged frame section is finally removed. The avoidance of a molding flash ridge allows the component to be suction-held by a suction needle at this housing surface.

Claims

1. A conductor strip arrangement for a molded electronic component (11), comprising at least one semiconductor element (5a-c) located on an electrically conducting conductor strip (1), and a housing (12) made of a molding material arranged around the conductor strip (1) and the at least one semiconductor element (5a-c) such that there are still sections (8) of the conductor strip (1) outside the housing (12), wherein a widened section (8.1) among the sections of the conductor strip (1) features a widening (10) such that the widened section (8.1) of the conductor strip (1) contacts an outer surface of housing (12) so as to prevent a mold material ridge (19) from being formed on the outer surface of the housing (12) at a location of the widened section, and wherein the widened section is not fixedly embedded in the housing so as to be free and removable from the housing.

2. The conductor strip arrangement according to claim 1, wherein the widened section (8, 8.1) of the conductor strip (1) features apertures (9).

3. The conductor strip arrangement according to claim 2, wherein lands (21) are located between the apertures (9).

4. The conductor strip arrangement according to claim 2, wherein the apertures (9) are implemented as longitudinal holes.

5. The conductor strip arrangement according to claim 1, wherein an edge of the widened section is directly adjacent to and flushly contacts the outer surface of the housing.

6. The conductor strip arrangement according to claim 1, wherein an edge portion of the widened section projects through the outer surface of the housing and into the molding material that forms the housing.

7. A process for molding a housing (12) of an electronic component (11) in a mold form, with the component (1) featuring an electrically conducting conductor strip (1) having connection pins (2) located to one side, and having a frame (8) including frame sections (8.1, 8.2) that is arranged to form the lateral boundary between top and bottom sections of the mold form and that has a transverse dimension slightly larger than a transverse dimension of the mold form, and comprising a step of molding a mold material around at least a portion of the electronic component in a mold cavity of the mold form to form the housing of the mold material, wherein a widened frame section (8.1) among the frame sections of the frame features a widening (10) that extends inwardly toward the electronic component sufficiently to at least reach a side boundary wall of the mold cavity of the mold form in order to prevent the formation of a mold material ridge (19) on the housing (12), and further comprising a step of removing the widened frame section from the housing.

8. The process according to claim 7, further comprising mounting the at least one semiconductor element (5a-c) on the conductor strip (1) by means of solder or an electrically conductive adhesive.

9. The process according to claim 7, further comprising electrically contacting the at least one semiconductor element (5a-c) and the conductor strip (1) with each other by means of bond wires (6) made of an aluminum or gold alloy.

10. The process according to claim 7, wherein the mold material is a synthetic material that is transparent within a specific wavelength range.

11. The process according to claim 7, wherein the step of removing the widened frame section from the housing (12) comprises a step of mechanically deforming the widened frame section so as to pull the widened frame section away from the housing.

12. The process according to claim 11, wherein the step of mechanically deforming the widened frame section (8.1) comprises embossing a deformation (16) therein.

13. The process according to claim 12, wherein the embossing of the deformation (16) is facilitated by providing apertures (9) in the widened frame section (8.1) of the conductor strip (1).

14. The process according to claim 11, wherein the deformation (16) is manufactured as a bead.

15. The process according to claim 11, wherein the deformation (16) is manufactured as a V-shaped bead.

16. The process according to claim 7, wherein the widened frame section is configured and arranged so that an edge of the widened frame section is directly adjacent to and flush with the side boundary wall of the mold cavity of the mold form.

17. The process according to claim 7, wherein the widened frame section is configured and arranged so that an edge portion of the widened frame section projects into the mold cavity of the mold form and is surrounded by the mold material during the molding step.

18. A molded electronics arrangement comprising:

an electrically conductive conductor strip including a chip mount section and frame sections around at least a portion of a perimeter of said chip mount section with frame spacing gaps between said chip mount section and said frame sections;

a semiconductor element mounted on said chip mount section of said conductor strip; and

a housing made of a molded material that is molded around said semiconductor element and said chip mount section of said conductor strip, and with said molded material also received in said spacing gaps;

wherein said frame sections include a projecting frame section that has an inner frame edge that projects toward said chip mount section, said frame spacing gaps include a projecting frame spacing gap defined between said chip mount section and said inner frame edge of said projecting frame section, said inner frame edge at least reaches a major outer surface of said housing and contacts said molded material, and said projecting frame section is not fixedly embedded in said molded material so as to be free and removable from said housing.

19. The molded electronics arrangement according to claim 18, wherein said inner frame edge is flush with and just contacts said major outer surface of said housing.

20. The molded electronics arrangement according to claim 19,

further comprising a mold including a first mold half and a second mold half enclosing a mold cavity therebetween;

and wherein;

said frame sections are arranged and held along a parting plane between said first mold half and said second mold half;

said chip mount section, said semiconductor element and said housing are received in said mold cavity; and

said inner frame edge flushly borders said mold cavity without projecting into said mold cavity.

21. The molded electronics arrangement according to claim 18, wherein said projecting frame section projects through said major outer surface of said housing, and said inner frame edge is recessed into said molded material forming said housing.

22. The molded electronics arrangement according to claim 21,

further comprising a mold including a first mold half and a second mold half enclosing a mold cavity therebetween;

and wherein;

said frame sections are arranged and held along a parting plane between said first mold half and said second mold half;

said chip mount section, said semiconductor element and said housing are received in said mold cavity; and

said inner frame edge projects into said mold cavity.

23. A method of making and further processing the molded electronics arrangement according to claim 18, comprising the steps:

a) providing said semiconductor element mounted on said chip mount section of said electrically conductive conductor strip;

b) arranging said conductor strip with said frame sections received along a parting plane between a first mold half and a second mold half defining therebetween a mold cavity containing said semiconductor element mounted on said chip mount section, wherein said mold halves include a cavity bounding wall that bounds said mold cavity;

c) closing said first and second mold halves to close said mold cavity, wherein said conductor strip is positioned relative to said mold halves so that a cavity spacing gap between said chip mount section and said cavity bounding wall adjacent to said projecting frame section is at least as large as said projecting frame spacing gap;

d) injecting said molded material into said mold cavity to mold said molded material around said semiconductor element and said chip mount section to form said housing, wherein said cavity bounding wall molds and forms said major outer surface of said housing;

e) opening said mold halves and removing said molded electronics arrangement; and

f) removing said projecting frame section from said housing.

24. The method according to claim 23, wherein said inner frame edge is flush with said cavity bounding wall without projecting into said mold cavity and said cavity spacing gap is equal to said projecting frame spacing gap in said step c).

25. The method according to claim 23, wherein said projecting frame section projects beyond said cavity bounding wall with said inner frame edge protruding into said mold cavity and said cavity spacing gap is greater than said projecting frame spacing gap in said step c).