Flip-chip assembly of protected micromechanical devices

• US 6,656,768 B2
• Filed: 10/30/2002
• Issued: 12/02/2003
• Est. Priority Date: 02/08/2001
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Thomas, Sunil
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US10/283,494
• Publication Number:
  US 20030052404A1
• Time in Patent Office: 398 Days
• Field of Search: 438/108, 438/106, 438/121, 438/116, 257/687, 257/692, 257/698, 257/778, 257/684
• US Class Current: 438/108
• CPC Class Codes: A43B 3/0026 for use in minefields; protecting from landmine blast; preventing landmines from being triggered
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/098 Arrangements not provided for in groups B81B2207/092 - B81B2207/097
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

A low-cost ceramic package, in land-grid array or ball-grid array configuration, for micromechanical components is fabricated by coating the whole integrated circuits wafer with a protective material, selectively etching the coating for solder ball attachment, singulating the chips, flip-chip assembling a chip onto the opening of a ceramic substrate, underfilling the gaps between the solder joints with a polymeric encapsulant, removing the protective material form the components, and attaching a lid to the substrate for sealing the package. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices. In all applications, the invention achieves technical advantages as well as significant cost reduction and yield increase.

Claims

1. A method of fabricating land-grid array devices for semiconductor chips having an integrated circuit including a plurality of micromechanical components configured in a plane in the central portion of said chip and a plurality of metallic terminals disposed in peripheral portions encircling said chip, comprising:

providing a wafer having a surface including a plurality of said chips;

coating said wafer surface with a protective material;

selectively etching said protective coating, exposing said terminals of each of said chips;

depositing one solder ball on each of said exposed terminals;

separating the resulting composite structure into discrete chips;

providing an electrically insulating substrate having first and second surfaces and an opening, said surfaces being substantially parallel to each other, a first plurality of metallic contact pads disposed on said first surface in proximity to said opening, and a second plurality of metallic contact pads disposed on said first surface remote from said opening;

mounting one of said discrete chips on said first plurality of substrate contact pads by forming solder joints, spaced apart by a gap;

controlling the height of said solder joints to maintain uniformity, thereby positioning said substrate in a plane parallel to said components plane;

filling said gap with a polymeric encapsulant, surrounding said opening by a continuous frame of encapsulant;

removing said protective material, thereby exposing the surfaces of said components; and

attaching a lid to said second substrate surface, thereby positioning said lid in a plane parallel to said plane of said components.

2. The method according to claim 1 wherein said steps of mounting, controlling and filling comprise the steps of:

aligning one of said discrete chips having said solder balls with said first plurality of substrate contact pads so that each of said balls is placed into alignment with one of said contact pads;

contacting said balls and said contact pads;

supplying thermal energy to said chip and said substrate, whereby said solder is reflowed to form solder joints and said chip is mounted to said substrate spaced apart by a gap, forming an assembly;

controlling the height of said solder joints to maintain uniformity, thereby positioning said substrate in a plane parallel to said components plane;

cooling said assembly from the reflow temperature to a temperature still elevated above ambient temperature and maintaining said elevated temperature at a substantially constant level;

filling said gap with a polymeric precursor at said elevated temperature, thereby surrounding said opening by a continuous frame of precursor;

supplying additional thermal energy for curing said polymeric precursor, thereby forming a polymeric encapsulant; and

cooling said assembly to ambient temperature.

3. The method according to claim 2 wherein said elevated temperature is between 90 and 130°

C.

4. The method according to claim 2 wherein said elevated temperature is approximately 100°

C.

5. The method according to claim 1 wherein said step of controlling the height of said solder joints comprises the steps of:

applying radiant energy to reach a liquid state of said solder balls;

contacting the smallest ball;

dwelling for metallurgical interaction;

establishing desired connection height; and

removing said radiant energy.

6. The method according to claim 1 further comprising the step of disposing a plurality of solder balls onto said second plurality of contact pads, thereby transforming said land-grid array device into a ball-grid array device.

7. The method according to claim 1 further comprising the step of depositing chemical compounds before attaching said lid to said second substrate surface.

8. The method according to claim 1 wherein said protective material is a layer of photoresist material as used in semiconductor photolithographic processes.

9. The method according to claim 1 wherein said step of selectively etching comprises the steps of masking, exposing and selective etching in accordance with the characteristics of said photoresist material employed.

10. The method according to claim 1 wherein said step of separating said composite structure comprises sawing.

11. The method according to claim 1 wherein said step of removing said protective material comprises dissolving said layer of photoresist material.