Delayed locked loop implementation in a synchronous dynamic random access memory

• US 6,657,919 B2
• Filed: 01/17/2003
• Issued: 12/02/2003
• Est. Priority Date: 10/06/1994
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Allan, Graham, Gillingham, Peter B., Foss, Richard C.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/348,062
• Publication Number:
  US 20030107944A1
• Time in Patent Office: 319 Days
• Field of Search: 365/194, 365/233, 365/189.05
• US Class Current: 365/233.16
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Claims

1. A synchronous memory comprising:

a clock input signal;

an adjustable delay line for generating a data output driving clock signal from the clock input signal; and

a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.

2. Synchronous memory as claimed in claim 1 herein the adjustable delay line is in a delay locked loop.

3. Synchronous memory as claimed in claim 2 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the circuit path taken by the clock input signal.

4. Synchronous memory as claimed in claim 2 wherein the adjustable delay line is a tapped delay line.

5. Synchronous memory as claimed in claim 4 wherein taps provide plural outputs of the delay line.

6. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is adapted to be disabled as a clock source to the data output buffer.

7. Synchronous memory as claimed in claim 1 wherein the adjustable delay line is used only to enable the data output buffer.

8. A synchronous dynamic random access memory comprising:

a clock input signal;

a delay locked loop comprising an adjustable delay line for generating a data output driving clock signal from the clock input signal; and

a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.

9. A method of enabling synchronous memory data output comprising:

delaying a clock input signal in an adjustable delay line to generate a data output driving clock signal; and

enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.

10. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is in a delay locked loop.

11. A method of enabling synchronous memory data output as claimed in claim 10 wherein the delay locked loop further comprises a delay model circuit which uses similar elements as the circuit path taken by the clock input signal.

12. A method of enabling synchronous memory data output as claimed in claim 10 wherein the adjustable delay line is a tapped delay line.

13. A method of enabling synchronous memory data output as claimed in claim 12 wherein taps provide plural outputs of the delay line.

14. A method of enabling synchronous memory data output as claimed in claim 9 further comprising disabling the adjustable delay line as a clock source for enabling output data.

15. A method of enabling synchronous memory data output as claimed in claim 9 wherein the adjustable delay line is used only to enable output data.

16. A method of enabling synchronous random access memory data output comprising:

delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and

enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.

17. A synchronous dynamic random access memory comprising:

means for delaying a clock input signal in an adjustable delay line of a delay locked loop to generate a data output driving clock signal; and

means for enabling output data with the driving clock signal, the data being output to an output terminal at the same time as or a minimum time following an edge of the clock input signal.