Delayed locked loop implementation in a synchronous dynamic random access memory

  • US 6,657,919 B2
  • Filed: 01/17/2003
  • Issued: 12/02/2003
  • Est. Priority Date: 10/06/1994
  • Status: Expired due to Fees
First Claim
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1. A synchronous memory comprising:

  • a clock input signal;

    an adjustable delay line for generating a data output driving clock signal from the clock input signal; and

    a data output buffer enabled by the driving clock signal for outputting data to an output terminal, the data being output to the output terminal at the same time as or a minimum time following an edge of the clock input signal.

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