P-i-n transit time silicon-on-insulator device

• US 6,660,616 B2
• Filed: 01/23/2002
• Issued: 12/09/2003
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: M2 Networks, Inc., Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Steinmann, Phillipp, Pinto, Angelo, Howard, Gregory E., Babcock, Jeffrey A.
• Primary Examiner(s): Hu, Shouxiang
• Assistant Examiner(s): VU, QUANG D
• Application Number:
  US10/055,436
• Publication Number:
  US 20020100950A1
• Time in Patent Office: 685 Days
• Field of Search: 257/104, 257/105, 257/106, 257/551, 257/603, 257/604, 257/656, 257/347, 257/283, 257/481, 438/91, 438/141, 438/149, 438/237, 438/328, 438/380, 438/479, 438/517
• US Class Current: 438/479
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Claims

1. A method of forming a transit time device in a semiconductor layer overlying an insulator layer, comprising the steps of:

masking the semiconductor layer to expose a first selected location of the semiconductor layer;

doping the exposed first selected location to a first conductivity type;

masking the semiconductor layer to expose a second selected location of the semiconductor layer, the first and second selected locations separated from one another by a distance;

doping the exposed second selected location to a second conductivity type, so that a portion of the semiconductor layer remaining between the first and second doped selected locations corresponds to an intrinsic region;

forming an isolation structure to surround the first and second doped selected locations and the intrinsic region;

doping the intrinsic region to a lightly-doped doping concentration relative to the first and second doped selected locations;

after the doping steps, forming an epitaxial layer over the semiconductor layer;

removing selected portions of the epitaxial layer, leaving first and second sinker structures overlying and in contact with the first and second doped selected locations of the semiconductor layer; and

doping the first and second sinker structures to the first and respectively, so that said first and second sinker structures become the first and second conductivity types, respectively,

wherein said first conductivity types is opposite to said second conductivity type.

2. The method of claim 1, wherein the step of forming an isolation structure comprises:

after the removing step, removing portions of the semiconductor layer surrounding the first and second doped selected locations and the intrinsic region;

then depositing an insulator at the locations of the removed portions of the semiconductor layer, and also the at the locations of the removed portions of the epitaxial layer.

3. The method of claim 1, wherein the removing step also leaves a charge injection sinker structure overlying and in contact with the intrinsic region;

and wherein the step of doping the first and second sinker structures also dopes the charge injection sinker structure to one of the first and second conductivity types.

4. The method of claim 3, wherein the step of forming an isolation structure comprises:

after the removing step, removing portions of the semiconductor layer surrounding the first and second doped selected locations and the intrinsic region;

then depositing an insulator at the locations of the removed portions of the semiconductor layer, and also at the locations of the removed portions of the epitaxial layer.

5. The method of claim 3, further comprising:

cladding a surface of each of the sinker structures and charge injection sinker structure with a refractory metal silicide.

6. The method of claim 5, further comprising:

cladding a surface of each of the sinker structures and charge injection sinker structure with a refractory metal silicide.