Process-scalable high spatial resolution and low bit resolution CMOS area image sensor

• US 6,665,012 B1
• Filed: 09/22/1998
• Issued: 12/16/2003
• Est. Priority Date: 09/22/1998
• Status: Expired due to Term

• Current Assignee: Pixim, Inc. (Sony Group Corp.)
• Original Assignee: Pixim, Inc. (Sony Group Corp.)
• Inventors: Deng, Zhonghan, Yang, Xiao D.
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US09/158,664
• Time in Patent Office: 1,911 Days
• Field of Search: H04/N.5335, 348/294, 348/300, 348/301, 348/302, 348/308, 250/208.1, 358/513
• US Class Current: 348/308
• CPC Class Codes: H04N 1/00281 with a telecommunication apparatus, e.g. a switched network of teleprinters for the distribution of text-based information, a selective call terminal details of transmission H04N1/00095; establishing a communication with one of a facsimile machine or another apparatus sharing a single line H04N1/32704; interfacing cordless telephone terminals with an accessory to increase the functionality of user interface H04M1/72409
• CPC Class Codes: H04N 1/00307 with a mobile telephone apparatus constructional features of portable telephone sets H04M1/0202; mobile radio systems H04W84/00
• CPC Class Codes: H04N 1/107 with manual scanning
• CPC Class Codes: H04N 1/195 the array comprising a two-dimensional array or a combination of two-dimensional arrays
• CPC Class Codes: H04N 2201/0458 Additional arrangements for improving or optimising scanning resolution or quality
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

The invention relates to a CMOS image sensor that an be embedded in portable imaging systems. This high spatial resolution and low bit resolution CMOS area image sensor not only enables portable imaging systems such as cellular fax phone, portable copy machines, barcode reader, but also it can be fabricated in standard digital CMOS processes, particularly at 0.35 micron and below. This invention also discloses several portable imaging systems using such a CMOS image sensor. This invention further discloses a CMOS image sensor that has variable spatial resolution and bit resolution. Starting as a high spatial resolution low-bit resolution image sensor, the high bit-resolution is achieved by combining information from a group of nearest-neighbor pixels into a single super-pixel via spatial oversampling. This variable CMOS image sensor can be used in a multiple function imaging device for both document and video imaging, or photography.

Claims

1. A process-scalable and resolution-variable image sensor comprises:

a plurality of sensor circuits configured in a two-dimensional array, each of said sensor circuits comprising a sensor pixel and an adjusting circuit, said sensor pixel producing an analog signal when being exposed to incident light, said adjusting circuit adjusting said analog signal in accordance with a predefined parameter, wherein said predefined parameter is selectively configurable to be different from parameters of adjusting circuits in adjacent sensor pixels to said sensor pixel; and

a column processor comprising a plurality of readout circuits, each of said readout circuits, coupled to an array of said sensor circuits, receiving said adjusted analog signal therefrom and converting said adjusted analog signal to a digital signal.

2. The process-scalable and resolution-variable image sensor as recited in claim 1,

wherein each of said readout circuits includes a comparator with a predefined threshold; and

wherein said comparator outputs said digital signal in a single bit format representing said adjusted analog signal being either higher or lower than said predefined threshold.

3. The process-scalable and resolution-variable image sensor as recited in claim 2, wherein said column processor combines a group of digital signals in said bit format into a single combined digital signal represented in a higher bit resolution and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

4. The process-scalable and resolution-variable image sensor as recited in claim 3,

wherein there are N by M said digital signals in said group;

said higher bit resolution is at least [1+0.5 log₂(N×

M)] bit precision and said reduced spatial resolution format is no more than 1/(N×

M).

5. The process-scalable and resolution-variable image sensor as recited in claim 1, further comprising:

a memory for storing code instructions; and

a digital signal processor;

coupled to said memory;

executing said code instructions to process digital signals from said column processor in accordance with a predefined requirement.

6. The process-scalable and resolution-variable image sensor as recited in claim 5, wherein said predefined requirement is related to facsimile communication standards so that said processed digital signals can be transmitted to a facsimile machine for printing.

7. The process-scalable and resolution-variable image sensor as recited in claim 6, wherein said digital signal processor is monolithically integrated with said sensor circuits.

8. The process-scalable and resolution-variable image sensor as recited in claim 1, wherein each of said readout circuits includes an analog-to-digital converter digitizing said adjusted analog signal to said digital signal.

9. The process-scalable and resolution-variable image sensor as recited in claim 8 further comprising:

a memory for storing code instructions; and

a digital signal processor, coupled to said memory;

executing said code instructions to combine a number of digital signals originating from a block of said sensor circuits to form a single digital signal represented in a higher bit resolution and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

10. The process-scalable and resolution-variable image sensor as recited in claim 9,

wherein said single bit format is a binary format;

and

wherein there are N by N said digital signals in said group;

said higher bit resolution is at least 0.5 log₂(N×

M) bit precision and said reduced spatial resolution format is no more than 1/(N×

M).

11. The process-scalable and resolution-variable image sensor as recited in claim 8, wherein said column processor combines a number of digital signals originating from a block of said sensor circuits to form a single digital signal represented in a higher bit and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

12. The process-scalable and resolution-variable image sensor as recited in claim 1, wherein said predefined parameter is a voltage applied onto said each of said sensor circuits so that said analog signal is amplified accordingly.

13. The process-scalable and resolution-variable image sensor as recited in claim 1, wherein said adjusting circuit adjusts said analog signal by adding a predefined voltage thereto so that said analog signal is escalated accordingly.

14. A process-scalable and resolution-variable image sensor comprises:

a plurality of sensor pixels arranged in a two-dimension array, each of said sensor pixels producing an analog signal when said sensor pixels are exposed to incident light; and

a column processor comprising a plurality of readout circuits, each of said readout circuits, coupled to a column of said sensor pixels outputting analog signals, comprising an adjusting circuit that adjusts each of said analog signals in accordance with a predefined parameter designated to said each of said readout circuits, before or during converting said each of said analog signals to a digital signal, wherein said predefined parameter is different from respective parameters in adjacent said readout circuits.

15. The process-scalable and resolution-variable image sensor as recited in claim 14,

wherein each of said readout circuits further comprises a comparator with a predefined threshold, said comparator receiving said adjusted analog signals from said adjusting circuit; and

wherein said comparator outputs digital signals, respectively, in a single bit format from said adjusted analog signals, said digital signals representing said adjusted analog signal being either higher or lower than said predefined threshold.

16. The process-scalable and resolution-variable image sensor as recited in claim 15 further comprising;

a memory for storing code instructions; and

a digital signal processor, coupled to said memory, executing said code instructions to process said digital signals in said single bit format from said column processor in accordance to a predefined application.

17. The process-scalable and resolution-variable image sensor as recited in claim 16, wherein said predefined application is related to facsimile communication standards so that said processed digital signals can be communicated to a facsimile machine for printing.

18. The process-scalable and resolution-variable image sensor as recited in claim 16, wherein said predefined application is to combine a number of digital signals originating from a block of said sensor circuits to form a single digital signal represented in a higher bit resolution and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

19. The process-scalable and resolution-variable image sensor as recited in claim 18,

wherein there are N by N said digital signals in said group;

said higher bit resolution is at least [1+0.5 log₂(N×

M)] bit precision and said reduced spatial resolution format is no more than 1/(N×

M).

20. The process-scalable and resolution-variable image sensor as recited in claim 19, wherein said digital signal processor is monolithically integrated with said sensor circuits.

21. The process-scalable and resolution-variable image sensor as recited in claim 14, wherein each of said readout circuits further comprises an analog-to-digital converter receiving said adjusted analog signals from said adjusting circuit and sequentially converting said adjusted analog signals to digital signals.

22. The process-scalable and resolution-variable image sensor as recited in claim 21 further comprising:

a memory for storing code instructions; and

a digital signal processor, coupled to said memory, executing said code instructions to combine a number of said digital signals originating from a block of said sensor circuits to form a single digital signal represented in a higher bit resolution and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

23. The process-scalable and resolution-variable image sensor as recited in claim 22,

wherein there are N by M said digital signals in said group;

said higher bit resolution is at least [1+0.5 log₂(N×

M)] bit precision and said reduced spatial resolution format is no more than 1/(N×

M).

24. A method for providing process-scalable and resolution-variable digital image signals from an image sensor, said method comprises:

generating image signals from an array of sensor circuits arranged in a two-dimensional array;

each of said sensor circuits comprising a sensor pixel generating one of said image signals when being exposed to incident light;

adjusting said image signals in accordance with an array of parameters, at least one of said parameters different from at least two of its immediate neighboring parameters; and

converting said adjusted image in a column processor signals into digital images.

25. The method as recited in claim 24;

wherein each of said sensor circuits further comprises an adjusting circuit that causes one of said image signals to be adjusted in accordance with one of said parameters.

26. The method as recited in claim 25;

wherein said adjusting circuit adds said one of said image signals a voltage signal appropriate to said one of said parameters so that said one of said image signals is escalated accordingly.

27. The method as recited in claim 25;

wherein said adjusting circuit is an amplifier applied thereon a voltage in accordance with one of said parameters so that said one of said image signals is amplified accordingly.

28. The method as recited in claim 24;

wherein said converting said adjusted image signals comprises;

comparing said adjusted image signals against a predefined threshold; and

generating said digital images.

29. The method as recited in claim 24;

wherein said converting said adjusted image signals comprises;

receiving columns of said adjusted image signals;

comparing, respectively and in parallel, said columns of said adjusted image signals against a predefined threshold; and

producing columns of said digital images.

30. The method as recited in claim 24;

wherein said converting said adjusted image signals comprises;

receiving columns of said adjusted image signals; and

digitizing, respectively and in parallel, said columns of said adjusted image signals into columns of said digital images.

31. The method as recited in claim 30;

said method further comprising;

combining blocks of said digital images with respect to said array of parameters into an array of new digital signals;

each of said new digital signals corresponding to one of said blocks of said digital images and represented in a higher bit resolution and reduced spatial resolution format in accordance with a set of rules related to said predefined parameter.

32. The method as recited in claim 31;

wherein there are N by M said digital signals in said group;

said higher bit resolution is at least [1+0.5 log₂(N×

M)] bit precision and said reduced spatial resolution format is no more than 1/(N×

M).

33. The method as recited in claim 24;

wherein said array of parameters are in accordance with a matrix of numerals to dither said image signals.

34. A method for providing process-scalable and resolution-variable digital image signals from an image sensor, said method comprises:

generating sensor signals from an array of sensor circuits arranged in a two-dimensional array;

each of said sensor circuits comprising a sensor pixel, an adjusting circuit and a comparator;

said sensor pixel generating one of said sensor signals when being exposed to incident light;

adjusting said sensor signals in accordance with an array of parameters, at least one of said parameters different from at least two of its immediate neighboring parameters; and

converting each of said adjusted sensor signals to one of said image signals representing said adjusted sensor signal being either higher or lower than a predefined threshold by using said comparator.

35. The method as recited in claim 34;

wherein said array of parameters cause to dither said sensor signals in accordance with a facsimile standard.

36. The method as recited in claim 35;

wherein said image signals can be output to a facsimile machine.

37. The method as recited in claim 34;

wherein each of said parameters is provided by a voltage applied onto a respective adjusting circuit in one of said pixel circuits.

38. The method as recited in claim 34;

wherein said array of parameters is configured as a two-dimensional matrix and titled repeatedly up to entire said image sensor.