Micro-machining

• US 6,670,212 B2
• Filed: 07/05/2001
• Issued: 12/30/2003
• Est. Priority Date: 09/12/1998
• Status: Expired due to Fees

• Current Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Original Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Inventors: McNie, Mark E., Nayar, Vishal
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/898,081
• Publication Number:
  US 20020017132A1
• Time in Patent Office: 908 Days
• Field of Search: 438/50, 438/51, 438/52, 438/53, 438/458, 438/739
• US Class Current: 438/52
• CPC Class Codes: G01C 19/56 Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces

Abstract

A method of fabricating a micro-mechanical sensor (101) comprising the steps for forming an insulating layer (6) onto the surface of a first wafer (4) bonding a second wafer (2) to the insulating layer (6), patterning and subsequently etching either the first (4) or second wafer (6) such that channels (18,20) are created in either the first (2) or second (4) wafer terminating adjacent the insulating layer (6) and etching the insulating layer (6) to remove portions of the insulating layer (6) below the etched wafer such that those portions of the etched wafer below a predetermined cross section, suspended portions (22), become substantially freely suspended above the un-etched wafer. This method uses Silicon on Insulator technology. Also disclosed is a micro-mechanical gyroscope structure (101) allowing an anisotropic silicon to be used to fabricate a sensor functioning as if fabricated from isotropic silicon.

Claims

1. A method of fabricating a micro-mechanical sensor comprising taking a first wafer with an insulating layer formed thereon and with a second wafer bonded to the insulating layer and

(a) patterning and subsequently etching one of either said first or second wafers such that channels are created in said etched wafer terminating adjacent to said insulating layer;

and

(b) etching said insulating layer to remove portions of said insulating layer adjacent said etched wafer such that those portions of said etched wafer below a predetermined size become substantially freely suspended above the other wafer

wherein said insulating layer between said first and said second wafers comprises at least one layer of undoped oxide and at least one layer of doped oxide.

2. A method according to claim 1 wherein the thickness of said insulating layer is substantially in the range 10 nm to 100 μ

m.

3. A method according to claim 1 wherein said second wafer is a substrate or handle wafer which is provided as a support for the micro-mechanical sensor.

4. A method according to claim 1 wherein the method comprises an additional step before step (a) of polishing said wafer to be etched (which may be either said first or second wafer) to the desired thickness.

5. A method according to claim 1 wherein a mask for the etch of step (a) is optimised so that areas to be etched have substantially equal cross sectional area.

6. A method according to claim 1 wherein suspensory ligaments are provided to join said suspended portions and a remainder of said etched wafer.

7. A method according to claim 1 wherein the method includes the step of cleaning the etch of said insulating layer with a vapour.

8. A method according to claim 7 wherein the structure being fabricated is held above substantially the boiling point of said vapour.

11. A method according to claim 1 wherein said first and second wafers are provided from a semi-conductor.

12. A method according to claim 1 which comprises providing integrated circuits in association with said sensor such that a sensor is provided on a single wafer with the necessary signal processing electronics.

13. A method according to claim 1 wherein there are provided two layers of undoped oxide sandwiching a layer of doped oxide.

14. A method according to claim 1 wherein dopants are included in the layer of doped oxide and include any one from the following list consisting of:

Phosphorous, Boron, Antimony, Arsenic, Germanium.

21. A method according to claim 1 wherein said insulating layer additionally comprises at least one Nitride layer.

22. A method according to claim 1 wherein the etch step (b) is timed such that some of said at least one undoped oxide layer remains as a protrusion.

23. A methods according to claim 1 wherein said insulating layer is provided by a deposition process.

9. A method of fabricating a micro-mechanical sensor comprising taking a first wafer with an insulating layer formed thereon and with a second wafer bonded to the insulating layer and

(a) patterning and subsequently etching one of either said first or second wafers such that channels are created in said etched wafer terminating adjacent to said insulating layer;

and

(b) etching said insulating layer to remove portions of said insulating layer adjacent said etched wafer such that those portions of said etched wafer below a predetermined size become substantially freely suspended above the other wafer

wherein some of the channels created in said etched wafer prior to the performing of step (b) are refilled with a refill material.

10. A method according to claim 9 wherein surface layers are laid across said refilled channel.

15. A method of fabricating a micro-mechanical sensor comprising taking a first wafer with an insulating layer formed thereon and with a second wafer bonded to the insulating layer and

(a) patterning and subsequently etching one of either said first or second wafers such that channels are created in said etched wafer terminating adjacent to said insulating layer;

and

(b) etching said insulating layer to remove portions of said insulating layer adjacent said etched wafer such that those portions of said etched wafer below a predetermined size become substantially freely suspended above the other wafer

wherein stress between the first and second wafer is reduced by providing said insulating layer as a series of at least three layers.

16. A method according to claim 15 wherein at least one of said at least three layers comprises an undoped oxide.

17. A method according to claim 15 wherein at least one of said at least three layers comprises a doped oxide.

18. A method according to claim 15 wherein at least one of said at least three layers comprises a nitride.

19. A method according to claim 15 wherein said series of at least three layers are deposited on said first wafer by the steps of depositing a compressive layer followed by a tensile layer.

20. A method according to claim 15 wherein said series of at least three layers are deposited on said first wafer by the steps of depositing a tensile layer followed by a compressive layer.