System, apparatus, method, and computer program for execution-order preserving uncached write combine operation

• US 6,671,747 B1
• Filed: 08/03/2000
• Issued: 12/30/2003
• Est. Priority Date: 08/03/2000
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Duluk, Jerome F. Jr., Benkual, Jack, Ho, Thomas Y.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US09/632,278
• Time in Patent Office: 1,244 Days
• Field of Search: 710/1, 710/5, 710/20, 710/31, 710/33, 710/36, 710/52, 710/65, 712/225, 709/223, 711/100, 711/147
• US Class Current: 710/1
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A mechanism that allows an application program running on a processor, to send data to a device using a medium that temporarily stores data and changes the order of the data dispatch on the way to the device. An inventive Random-In-First-Out (RIFO) buffer or memory device that restores the original order is provided. Several alternative approaches for implementing the RIFO control mechanisms for write efficiency and correctness. Method for use in conjunction with a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by the write instructions to at least one hardware device coupled to the host processor for receiving the symbols from the host processor, where the method preserves a predetermined order in which the symbols are received by the hardware device. Method includes sending a symbol from the host processor to a storage with an identifier indicating a symbol ordering relative to other of the symbols, storing the symbol and the indicator in the storage, and altering the order of dispatch of the symbols from the storage to the hardware device based on the indicator so that the symbols are received by the hardware device in the predetermined order independent of the order in which the symbols were communicated by the host processor. The invention also provides numerous embodiments of system, apparatus, method, computer program, and computer program product associated with the inventive concept.

Claims

1. In a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by said write instructions to at least one hardware device coupled to said host processor for receiving said symbols from said host processor, a method for preserving a predetermined order in which said symbols are received by said hardware device, said method comprising steps of:

sending a symbol from said host processor to a storage with an identifier indicating a symbol ordering relative to other of said symbols;

storing said symbol and said indicator in said storage; and

altering the order of dispatch of said symbols from said storage to said hardware device based on said indicator so that said symbols are received by said hardware device in said predetermined order independent of the order in which said symbols were communicated by said host processor.

2. The method in claim 1, wherein said indicator is a bit associated with an address.

3. The method in claim 1, further including step of:

executing a write fence operation in said host processor when a particular first symbol is intended to be received by said hardware device before said hardware device receives a second symbol.

4. The method in claim 3, wherein said indicator is a bit associated with an address and said bit has a first state and a second state;

and further including step of;

changing the state of said bit associated with said address from a current state to the other state every time said step of executing a write fence operation is preformed.

5. In a data processing system having a host processor executing write instructions and communicating results in the form of symbols generated by said write instructions to at least one hardware device coupled to said host processor for receiving said symbols from said host processor, a method for preserving a predetermined order in which said symbols are received by said hardware device, said method comprising steps of:

sending a said symbol from said host processor to a storage with an address indicating a symbol ordering relative to other of said symbols;

storing said sent symbol at a location in said storage if a flag indicator associated with said location indicates said storage does not have valid data at said address, said location being associated with said address;

waiting to store said sent symbol at said location in said storage if said flag indicator associated with said location indicates said storage contains a valid symbol at said location;

reading, in a sequential location manner, a next symbol from said storage at a next location if a flag indicator associated with said next location indicates said storage contains said valid symbol at said next location; and

waiting to read from said next location if said flag indicator associated with said next location indicates said storage does not contain a said valid symbol at said next location.

6. The method in claim 5, wherein the step of reading, changes said flag indicator associated with said next location from indicating said storage contains a valid symbol to indicating said storage does not contain a valid symbol.

7. The method in claim 5, wherein the step of waiting to store further comprises putting said sent symbol in a first-in-first-out memory, said first-in-first-out memory storing a plurality of said sent symbols.