Solid-state imaging device and method for driving the same

• US 6,674,471 B1
• Filed: 05/28/1999
• Issued: 01/06/2004
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Masuyama, Masayuki
• Primary Examiner(s): Christensen, Andrew
• Assistant Examiner(s): GENCO, BRIAN C
• Application Number:
  US09/321,581
• Time in Patent Office: 1,684 Days
• Field of Search: 348/294, 348/312, 348/302, 257/223, 257/229, 257/230, 327/407, 250/208.1
• US Class Current: 348/312
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H04N 25/623 by evacuation via the output or reset lines
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A solid-state imaging device includes an imaging area including a plurality of pixels arranged in columns and rows, and peripheral circuitry for selecting at least one of the pixels. Each said pixel includes: a photoelectric transducer for creating electric charges by photoelectric conversion and storing the charges therein; means for storing the charges read out from the photoelectric transducer; a transfer electrode, provided between the photoelectric transducer and the storage means, for reading out the charges from the photoelectric transducer to the storage means; an amplifier for sensing a variation in potential in the storage means; and a reset electrode for discharging the charges, stored in the storage means, to a power supply, thereby resetting the potential in the storage means. The peripheral circuitry includes a selector for generating first and second control signals, which are applied to the transfer and reset electrodes, respectively, to control the heights of first and second electrical barriers under the transfer and reset electrodes, respectively. The selector includes a bank of multi-stage inverters operative upon the application of first and second power supply voltages thereto. The second power supply voltage is lower than the first power supply voltage. Some of the inverters on the last stage generate biased output signals to be supplied as the first and second control signals.

Claims

1. A solid-state imaging device comprising:

an imaging area including a plurality of pixels arranged in columns and rows; and

peripheral circuitry for selecting at least one of the pixels,

wherein each said pixel includes;

a photoelectric transducer for creating electric charges by converting incoming light into electric energy and for storing the charges therein;

means for storing the charges that have been read out from the photoelectric transducer;

a transfer electrode, provided between the photoelectric transducer and the storage means, for reading out the charges from the photoelectric transducer to the storage means;

an amplifier for sensing a variation in potential in the storage means; and

a reset electrode for discharging the charges, which have been stored in the storage means, to a power supply, thereby resetting the potential in the storage means, and

wherein the peripheral circuitry includes a selector for generating first and second control signals, the first control signal being applied to the transfer electrode to control the height of a first electrical barrier under the transfer electrode, the second control signal being applied to the reset electrode to control the height of a second electrical barrier under the reset electrode,

wherein the selector includes a bank of multi-stage inverters operative upon the application of first and second power supply voltages thereto, the second power supply voltage being lower than the first power supply voltage, some of the inverters on the last stage generating biased output signals to be supplied as the first and second control signals, and

wherein at least two different voltages are applied as the first power supply voltage to the bank of multi-stage inverters, the first power supply voltage applied to the last-stage inverters being higher than the first power supply voltage applied to the other inverters of the bank.

2. A solid-state imaging device comprising:

an imaging area including a plurality of pixels arranged in columns and rows; and

peripheral circuitry for selecting at least one of the pixels,

wherein each said pixel includes;

a photoelectric transducer for creating electric charges by converting incoming light into electric energy and for storing the charges therein;

an amplifier for sensing a variation in potential in the photoelectric transducer; and

a reset electrode for discharging the charges, which have been stored in the photoelectric transducer, to a power supply, thereby resetting the potential in the photoelectric transducer, and

wherein the peripheral circuitry includes a selector for generating a control signal to be applied to the reset electrode to control the height of an electrical barrier under the reset electrode,

wherein the selector includes a bank of multi-stage inverters operative upon the application of first and second power supply voltages thereto, the second power supply voltage being lower than the first power supply voltage, some of the inverters on the last stage generating a biased output signal to be supplied as the control signal, and

wherein at least two different voltages are applied as the first power supply voltage to the bank of multi-stage inverters, the first power supply voltage applied to the last-stage inverters being higher than the first power supply voltage applied to the other inverters of the bank.

3. A solid-state imaging device comprising

a plurality of pixels, and

peripheral circuitry for selecting at least one of the pixels,

wherein each said pixel includes

information storage for storing therein electric charges created by photoelectric conversion, and

a reset device, responsive to a control signal, for varying the height of an electrical barrier existing between the information storage and a power supply, thereby discharging the electric charges, which have been stored in the information storage, to the power supply, and

wherein the peripheral circuitry includes a selector for generating the control signal,

wherein the selector includes a bank of multi-stage inverters operative upon the application of first and second power supply voltages thereto, the second power supply voltage being lower than the first power supply voltage, some of the inverters on the last stage generating a biased output to be supplied as the control signal to the reset device, and

wherein at least two different voltages are applied as the first power supply voltage to the bank of multi-stage inverters, the first power supply voltage applied to the last-stage inverters being higher than the first power supply voltage applied to the other inverters of the bank.

4. The solid-state imaging device of claim 3, wherein the information storage includes a photoelectric transducer.

5. The solid-state imaging device of claim 3 or 4, wherein each said last-stage inverter of the selector is a CMOS inverter including an enhancement-mode n-channel MOS transistor and a depletion-mode p-channel MOS transistor.

8. The solid-state imaging device of claim 3 or 4, wherein each said last-stage inverter is a CMOS inverter including n-channel and p-channel MOS transistors.

9. The solid-state imaging device of claim 4, wherein each said pixel includes a transfer electrode provided between the photoelectric transducer and the reset device, and

wherein responsive to a second control signal, the transfer electrode varies the height of an electrical barrier existing under the transfer electrode, thereby discharging the electric charges, which have been stored in the photoelectric transducer, to the power supply.

10. The solid-state imaging device of claim 9, wherein the selector includes a second bank of multi-stage inverters operative upon the application of the first and second power supply voltages thereto, a last-stage inverter belonging to the second bank generating a biased output to be supplied as the control signal to the transfer electrode.

11. The solid-state imaging device of claim 10, wherein the last-stage inverter of the second bank is a CMOS inverter including an enhancement-mode n-channel MOS transistor and a depletion-mode p-channel MOS transistor.

12. The solid-state imaging device of claim 10, wherein at least two different voltages are applied as the first power supply voltage to the second bank of multi-stage inverters, the first power supply voltage applied to the last-stage inverters of the second bank being higher than the first power supply voltage applied to the other inverters of the second bank.

13. The solid-state imaging device of claim 10, wherein at least two different voltages are applied as the second power supply voltage to the second bank of multi-stage inverters, the second power supply voltage applied to the last-stage inverters of the second bank being higher than the second power supply voltage applied to the other inverters of the second bank.

14. The solid-state imaging device of claim 10, wherein the first power supply voltage applied to the last-stage inverter of the second bank is higher than a third power supply voltage received by the other inverters of the second bank during a selected interval only.

15. The solid-state imaging device of claim 14, wherein the selected interval is included in a horizontal blanking interval.

16. A method for driving the solid-state imaging device recited in one of claims 3-5 and 6-8, the method comprising the steps of:

creating electric charges by photoelectric conversion to store the charges in the information storage; and

increasing a level of the control signal, generated by the selector, like pulses to make the reset device reset the charges in the information storage.

17. A method for driving the solid-state imaging device recited in one of claims 9 to 15, the method comprising the steps of:

creating electric charges by photoelectric conversion to store the charges in the photoelectric transducer;

increasing a level of the first control signal, generated by the selector, like pulses to make the reset device reset the charges existing between the transfer electrode and the reset device; and

increasing a level of the second control signal, generated by the selector, like pulses to transfer the charges in the photoelectric transducer to between the transfer electrode and the reset device via the transfer electrode.

6. A solid-state imaging device comprising

a plurality of pixels, and

peripheral circuitry for selecting at least one of the pixels,

wherein each said pixel includes

information storage for storing therein electric charges created by photoelectric conversion, and

a reset device, responsive to a control signal, for varying the height of an electrical barrier existing between the information storage and a power supply, thereby discharging the electric charges, which have been stored in the information storage, to the power supply, and

wherein the peripheral circuitry includes a selector for generating the control signal,

wherein the selector includes a bank of multi-stage inverters operative upon the application of first and second power supply voltages thereto, the second power supply voltage being lower than the first power supply voltage, some of the inverters on the last stage generating a biased output to be supplied as the control signal to the reset device, and

wherein the first power supply voltage applied to the last-stage inverters is higher than a third power supply voltage applied to the other inverters of the bank during a selected interval only.

7. The solid-state imaging device of claim 6, wherein the selected interval is included in a horizontal blanking interval.