Integrated circuit with multiple processing cores

• US 6,675,284 B1
• Filed: 08/20/1999
• Issued: 01/06/2004
• Est. Priority Date: 08/21/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Warren, Robert
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/378,909
• Time in Patent Office: 1,600 Days
• Field of Search: 709/250, 714/30, 714/718, 714/722, 712/227, 712/38, 710/306, 710/309
• US Class Current: 712/38
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning

Abstract

An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received. The adaptor further includes receive circuitry having circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, circuitry for converting the bit sequence into parallel data and control signals for the on-chip functional circuitry and circuitry for transmitting parallel data and control signals on the communication channel identified by said channel identification bits.

Claims

1. An integrated circuit comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores, each processing core associated with a respective communication channel;

c) a data adaptor that is in communication with the processing cores by the respective communication channels and is connectable to the input and output pins, the data adaptor comprising;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits.

2. The integrated circuit of claim 1 wherein the receive circuitry comprises a decoder for decoding an event sequence of said serial bits, said event sequence including said channel identification bits.

3. The integrated circuit of claim 1 wherein the transmit circuitry includes an event generator which generates an event sequence of bits to identify the communication channel on which data is being transmitted.

4. The integrated circuit of claim 3 wherein the event generator is only operable to generate an event sequence when the instant communication channel is switched to an alternative communication channel.

5. The integrated circuit of claim 1 wherein each processing core includes at least one autonomously operating processor.

6. The integrated circuit of claim 1 wherein each processing core includes a message converter which formulates messages to be transmitted off-chip via the data adaptor and decodes messages which are received on-chip via the data adaptor.

7. The integrated circuit of claim 1 wherein each processing core includes on-chip memory.

8. The integrated circuit of claim 1 wherein each processing core includes a bus system for communicating with off-chip memory.

9. The integrated circuit of claim 1 wherein each processing core comprises a set of registers holding information for diagnostic purposes, said registers being accessible from off-chip via the data adaptor and the communication channel associated with that processing core.

10. The integrated circuit of claim 1 which further comprises a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to on-chip test logic in a first mode of operation and connectable to the data adaptor in a second mode of operation.

11. A computer system comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores;

c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits;

(d) at least two independently operating off-chip processors; and

(e) an off-chip host communications adaptor connected to the off-chip processors and configured to convert parallel data and control signals from the off-chip processors into a sequence of serial bits for communicating on-chip.

12. A computer system comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores;

c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits;

(d) an off-chip host processor operating independently of at least two debugging applications; and

(e) an off-chip host communications adaptor connected to receive messages from the host processor and to convert said messages from a form of parallel data and control signals into a sequence of serial bits for communicating on-chip.

13. A computer system comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores;

c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, the data adaptor comprising;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identified by said channel identification bit;

(d) an off-chip host processor operating a debugging application with independently operable interface modules; and

(e) a host communications adaptor connected to the host processor and operable to convert messages in a form of parallel data and control signals into a sequence of serial bits for communication on-chip.

14. A method of effecting communication of messages from one of a plurality of independent processing cores on an integrated circuit to an off-chip host processor, each of the processing cores associated with a respective communication channel, wherein:

a) said one independent processing core formulates a message including a message identifier denoting the nature of the message and a channel identifier denoting the communication channel by which the independent processing core seeks to communicate the message;

b) the message is communicated via the identified communication channel to a data adaptor that adapts the message into a format suitable for communication off-chip;

c) when an alternative independent processing core seeks to communicate a message, a new communication channel is identified for the alternative independent processing core and an event message is generated for transmission off-chip identifying the alternative communication channel.

15. The method according to claim 14, wherein when a message is received on-chip, its channel identifier is decoded and the message is conveyed to the communication channel identified by the channel identifier so that the message is transmitted to a correct one of the independent processing cores.

16. An integrated circuit, comprising:

a plurality of independent processing cores, each independent processing core configured to formulate a first message that includes a first message identifier denoting the nature of the first message and a channel identifier denoting a first communication channel by which the independent processing core seeks to communicate the first message off-chip;

a data adaptor coupled to the plurality of independent processing cores, the data adaptor configured to receive the first message via the identified first communication channel and to adapt the message for communication off-chip, the data adaptor further configured to receive a second message from a second independent processing core denoting a second communication channel and to generate an event message for transmission off-chip identifying the second communication channel.

17. The circuit of claim 16 wherein the data adaptor is further configured to receive an off-chip message and decode the off-chip message for transmission via a communication channel identified by the channel identifier for receipt by one of the plurality of independent processing cores.

18. The circuit of claim 17 wherein the data adaptor is further configured to receive parallel and serial data and to convert the same to serial and parallel data, respectively.

19. The circuit of claim 18, further comprising diagnostic registers associated with each of the plurality of independent processing cores and configured to be accessible from off-chip via the data adaptor.

20. The circuit of claim 18, further comprising a test access port controller configured to effect communication of serial data across a circuit boundary via input and output pins, the test access port controller being connectable to test logic in the integrated circuit in a first mode of operation and connectable to the data adaptor in a second mode of operation.

21. An integrated circuit comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores;

c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, wherein the data adaptor comprises;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identification by said channel identification bit;

wherein the receive circuitry comprises a decoder for decoding an event sequence of said serial bits, said event sequence including said channel identification bits;

wherein the event generator is only operable to generate an event sequence when the instant communication channel is switched to an alternative communication channel.

22. An integrated circuit comprising:

a) a serial data input pin and a serial data output pin;

b) on-chip functional circuitry comprising at least two processing cores;

c) a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, wherein the data adaptor comprises;

i) transmit circuitry including circuitry for receiving parallel data and control signals from said on-chip functional circuitry;

ii) circuitry for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received;

iii) receive circuitry including circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits;

iv) circuitry for converting said sequence into parallel data and control signals for said on-chip functional circuitry; and

v) circuitry for transmitting said parallel data and control signals on the communication channel identification by said channel identification bit, under control of the flow control bits.

23. The circuit of claim 22, wherein the data adapter is configured to respond to start and stop bits in the flow control bits to only enable the flow of serial bits when capacity is available to receive the flow of serial bits.