Antifuse structure and method of making

• US 6,677,220 B2
• Filed: 03/12/2003
• Issued: 01/13/2004
• Est. Priority Date: 01/16/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Tran, Long
• Application Number:
  US10/386,597
• Publication Number:
  US 20030173592A1
• Time in Patent Office: 307 Days
• Field of Search: 438/131, 438/257, 438/467, 438/600, 438/957, 257/50, 257/530
• US Class Current: 438/467
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

An antifuse structure has an antifuse between first and second thermal conduction regions. Each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity. The portion having low thermal conductivity is between the respective portion of high thermal conductivity and the antifuse.

Claims

1. A method, comprising the step of:

forming an antifuse between first and second thermal conduction regions, wherein;

each of the first and second thermal conduction regions has a portion of low thermal conductivity and a portion of high conductivity; and

the portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the antifuse.

2. The method as defined in claim 1, wherein the portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of the portion of high thermal conductivity.

3. A memory structure comprising an antifuse structure made by the method of claim 1.

4. A memory device selected from the group consisting of a WORM memory device and a one time programmable memory device, comprising the memory structure as defined in claim 3.

5. A memory apparatus that is selected from the group consisting of a digital film and a memory card, comprising the memory device as defined in claim 4.

6. A method of making a memory structure, the method comprising the steps of:

forming a bottom row line;

forming a bottom antifuse above the bottom row line with a thermal interface there between;

forming a bottom control element about the bottom antifuse;

forming a column line over the bottom control element;

forming a top antifuse over the column line with a thermal interface there between;

forming a top control element over the top antifuse; and

forming a top row line over the top control element.

7. The method as defined in claim 6, wherein:

each of the top and bottom antifuses is between top and bottom thermal conduction regions;

each of the top and bottom thermal conduction regions has a portion of low thermal conductivity and a portion of high thermal conductivity;

each said portion of high thermal conductivity is selected from the group consisting of the column line and the bottom and top row lines; and

each said portion having low thermal conductivity is between the respective said portion of high thermal conductivity and the respective one of the top and bottom antifuses.

8. The method as defined in claim 7, wherein each said portion having low thermal conductivity has a thermal conductivity less by about an order of magnitude than that of each said portion of high thermal conductivity.

9. A method of making a memory structure, the method comprising the steps of:

forming a memory cell over a substrate by;

forming a patterned row line over the substrate;

forming an electrical insulator upon the patterned row and having a plurality of via plugs therein that is in electrical communication with the patterned row line;

forming a first electrode upon the electrical insulator and the via plugs therein;

forming a plurality of patterned stacks upon the first electrode each including an antifuse layer and a control element;

forming a dielectric fill upon the first electrode and interfacing the plurality of patterned stacks;

forming a second electrode upon the patterned stacks and the dielectric fill;

forming a second electrical insulator upon the second electrode and having a plurality of via plugs therein; and

forming a patterned column line upon the second electrical insulator and the via plugs therein.

10. The method as defined in claim 9, further comprising the step of forming a plurality of said memory cell each being vertically offset one from another by an interlayer dielectric.

11. The method as defined in claim 9, wherein:

the row line and the column line each comprise aluminum or an alloy thereof;

the via plugs each comprise refractory metal or alloy thereof;

the dielectric fill comprises silicon dioxide;

at least a portion of the control element comprises lightly doped amorphous or microcrystalline silicon; and

the antifuse layer comprises alumina.

12. The method as defined in claim 9, wherein the control element is selected from the group consisting of a diode and a tunnel junction.

13. A method of making a memory structure, the method comprising the steps of:

forming a first electrical insulator upon a first patterned row, the first electrical insulator having a plurality of via plugs therein that are in electrical communication with the first patterned row line;

forming a first electrode upon the first electrical insulator and the via plugs therein;

forming a plurality of first patterned stacks upon the first electrode each including an antifuse layer and a control element;

forming a first dielectric fill upon the first electrode and interfacing the plurality of first patterned stacks;

forming a second electrode upon the first patterned stacks;

forming a second electrical insulator upon the second electrode, the second electrical insulator having a plurality of via plugs therein; and

forming a patterned column line in electrical communication with the via plugs in the second electrical insulator;

forming a third electrical insulator upon the patterned column line and having a plurality of via plugs therein that are in electrical communication with the patterned column line;

forming a third electrode upon the third electrical insulator and the plurality of via plugs therein;

forming a plurality of second patterned stacks upon the third electrode each including an antifuse layer and a control element;

forming a second dielectric fill upon the third electrode and interfacing the plurality of second patterned stacks;

forming a fourth electrode upon the second dielectric fill;

forming a fourth electrical insulator upon the fourth electrode, the fourth electrical insulator having a plurality of via plugs therein that are in electrical communication with the fourth electrode; and

forming a second patterned row line over the fourth electrical insulator and in electrical communication with the via plug in the fourth electrical insulator.

14. The method as defined in claim 13, wherein:

the first and second row lines and the column line each comprise aluminum or an alloy thereof;

the via plugs each comprises a refractory metal or alloy thereof;

the first and second dielectric fills each comprise silicon dioxide;

at least a portion of each said control element comprises lightly doped amorphous or microcrystalline silicon; and

the first and second antifuse layers each comprise alumina.

15. The method as defined in claim 13, wherein each said control element is selected from the group consisting of a diode and a tunnel junction.