Semiconductor integrated circuit

• US 6,677,797 B2
• Filed: 12/21/2001
• Issued: 01/13/2004
• Est. Priority Date: 12/26/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yoshida, Masako, Ohuchi, Kazunori, Fuse, Tsuneaki, Kameyama, Atsushi
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/023,947
• Publication Number:
  US 20020080663A1
• Time in Patent Office: 753 Days
• Field of Search: 327/544, 327/333, 327/403, 327/407, 327/404, 327/81, 326/38, 326/40, 326/41, 326/80
• US Class Current: 327/333
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

An integrated circuit has first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a high threshold value, while the second logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a low threshold value. An output switch circuit intervenes between the p-type FET and n-type FET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.

Claims

1. A semiconductor integrated circuit comprising:

a first logic circuit which has a first input terminal and comprising a first logic block including a p-type FET with a threshold voltage of Vtp1 and a first inverted-logic block including an n-type FET with a threshold voltage of Vtn1, said first logic block and said first inverted-logic block being connected between a first power supply with a potential V1 and a reference potential;

a second logic circuit which has the same logic function as that of said first logic circuit, said second logic circuit having a second input terminal connected to said first input terminal and comprising a second logic block including a p-type FET with a threshold voltage of Vtp2 (Vtp2<

Vtp1) and a second inverted-logic block including an n-type FET with a threshold voltage of Vtn2 (Vtn2<

Vtn1), said second logic block and said second inverted-logic block being connected between a second power supply with a potential of V2 (V2<

V1) and said reference potential; and

an output switch circuit which intervenes between said first logic block and said first inverted-logic block in said first logic circuit and between said second logic block and said second inverted-logic block in said second logic circuit and which has a control signal terminal to which a control signal is inputted and an output terminal from which one of an output of said first logic circuit and an output of said second logic circuit is outputted according to said control signal.

2. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit sets one of said first logic circuit and said second logic circuit to a low impedance and the other to a high impedance and outputs said output of said one of said first logic circuit and said second logic circuit set to said low impedance to said output terminal.

3. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit includes

a first switch circuit comprising a first p-type FET and a first n-type FET connected in series between said first logic block and said first inverted-logic block in said first logic circuit, and

a second switch circuit comprising a second p-type FET and a second n-type FET connected in series between said second logic block and said second inverted-logic block in said second logic circuit, a connection node of said first p-type FET and said first n-type FET and a connection node of said second p-type FET and said second n-type FET being connected to said output terminal, and

when said first p-type FET and said first n-type FET are on according to said control signal, said second p-type FET and said second n-type FET are off, and when said first p-type FET and said first n-type FET are off, said second p-type FET and said second n-type FET are on.

4. The semiconductor integrated circuit according to claim 3, wherein said control signal to switch said output is inputted to gates of said first p-type FET of said first switch circuit and said second n-type FET of said second switch circuit and an inverted signal of said control signal is inputted to gates of said first n-type FET of said first switch circuit and said second p-type FET of said second switch circuit.

5. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit comprises a first switch circuit where a first p-type FET and a first n-type FET are connected in series between said first logic block and said first inverted-logic block in said first logic circuit, a connection node of said first p-type FET and said first n-type FET being connected to said output terminal, and a second switch circuit where a second and a third n-type FET are connected in series between said second logic block and said second inverted-logic block in said second logic circuit, a connection node of said second and said third n-type FET being connected to said output terminal, and

when each of said FETs in one of said first switch circuit and said second switch circuit is on according to said control signal, each of said FETs in the other switch circuit is off.

6. The semiconductor integrated circuit according to claim 5, wherein said control signal is inputted to gates of said first p-type FET of said first switch circuit and said second and said third n-type FET of said second switch circuit and an inverted signal of said control signal is inputted to a gate of said first n-type FET of said first switch circuit.

7. The semiconductor integrated circuit according to claim 1, wherein each of said first and said second logic circuit functions as an inverter.

8. A semiconductor integrated circuit which uses the semiconductor integrated circuit of claim 7 as an inverter section of a flip-flop.

9. The semiconductor integrated circuit according to claim 8, wherein said second power supply is connected via a switching transistor to said second logic circuit and, when said output switch circuit selects said output of said first logic circuit, said second logic circuit is disconnected from said second power supply.

10. The semiconductor integrated circuit according to claim 1, wherein each of said first and said second logic circuit is one selected from the group consisting of a NAND gate, a NOR gate and a combined gate configuration.

11. A semiconductor integrated circuit comprising:

a first switching gate to which an input signal is supplied;

a master flip-flop which includes a semiconductor integrated circuit of claim 1 and to which an input signal is inputted via said first switching gate;

a second switching gate to which an output signal of said master flip-flop is supplied;

a slave flip-flop which includes a semiconductor integrated circuit of claim 1 and to which said output signal of said master flip-flop is inputted via said second switching gate; and

a buffer circuit which includes a semiconductor integrated circuit of claim 1 and controls said first and said second switching gate.

12. A semiconductor integrated circuit comprising:

a first logic circuit which has a first input terminal and comprising a first logic block including a p-type FET with a threshold voltage of Vtp1 and a first inverted-logic block including an n-type FET with a threshold voltage of Vtn1, said first logic block and said first inverted-logic block being connected between a first power supply with a potential of V1 and a reference potential;

a second logic circuit which has a different logic function from that of said first logic circuit, the second logic circuit having a second input terminal and comprising a second logic block including a p-type FET with a threshold voltage of Vtp2 (Vtp2<

Vtp1) and a second inverted-logic block including an n-type FET with a threshold voltage of Vtn2 (Vtn2<

Vtn1), said second logic block and said second inverted-logic block being connected between a second power supply with a potential of V2 (V2<

V1) and said reference potential; and

an output switch circuit which intervenes between said first logic block and said first inverted-logic block in said first logic circuit and between said second logic block and said second inverted-logic block in said second logic circuit and which has a control signal terminal to which a control signal is inputted and an output terminal from which one of an output of said first logic circuit and an output of said second logic circuit is outputted according to said control signal.

13. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit outputs a constant potential.

14. The semiconductor integrated circuit to claim 12, wherein said output switch circuit switches one of said first logic circuit and said second logic circuit to a low impedance and the other to a high impedance and outputs said output of said one of said first logic circuit and said second logic circuit switched to said low impedance to said output terminal.

15. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit includes

a first switching p-type FET and a first switching n-type FET connected in series between said first logic block and said first inverted-logic block in said first logic circuit, and

a second switching p-type FET and a second switching n-type FET connected in series between said second logic block and said second inverted-logic block in said second logic circuit, a connection node of said first switching p-type FET and said first switching n-type FET and a connection node of said second switching p-type FET and said second switching n-type FET being connected to said output terminal, and

when said first switching p-type FET and said first switching n-type FET are on according to said control signal said second switching p-type FET and said second switching n-type FET are off, and when said first p-type FET and said first n-type FET are off, said second p-type FET and said second n-type FET are on.

16. The semiconductor integrated circuit according to claim 15, wherein said control signal to switch the output is inputted to gates of said first switching p-type FET and said second switching n-type FET and an inverted signal of said control signal is inputted to gates of said first switching n-type FET and said second switching p-type FET.

17. The semiconductor integrated circuit according to claim 12, wherein said output switch circuit is composed of a first switch circuit where a first p-type FET and a first n-type FET are connected in series between said first logic block and said first inverted-logic block in said first logic circuit, a connection node of said first p-type FET and said first n-type FET being connected to said output terminal, and a second switch circuit where a second and a third n-type FET are connected in series between said second logic block and said second inverted-logic block in said second logic circuit, a connection node of said second and said third n-type FET being connected to said output terminal, and

when each of said FETs in one of said first switch circuit and said second switch circuit is on according to said control signal, each of said FETs in the other switch circuit is off.

18. The semiconductor integrated circuit according to claim 17, wherein said control signal is inputted to gates of said first p-type FET of said first switch circuit and said second and said third n-type FET of said second switch circuit and an inverted signal of said control signal is inputted to a gate of said first n-type FET of said first switch circuit.