Semiconductor integrated circuit device

• US 6,677,803 B1
• Filed: 08/21/2002
• Issued: 01/13/2004
• Est. Priority Date: 08/21/2002
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Chiba, Tadashi
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US10/224,420
• Time in Patent Office: 510 Days
• Field of Search: 327/530, 327/534, 327/535, 327/537
• US Class Current: 327/534
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A semiconductor integrated circuit device which has a low power consumption in a static state. A first NMOS transistor includes a gate connected to an input, a source connected to ground, and a drain connected to an output. A second NMOS transistor includes a gate connected to the power supply, and a drain and source, one connected to the input terminal and the other to the first NMOS transistor'"'"'s body. A first PMOS transistor includes a gate connected to the input, a source connected to a power supply, and a drain connected to the output. A second PMOS transistor includes a gate connected to ground, and a drain and source, one connected to the input terminal and the other to the first PMOS transistor'"'"'s body. Also, the second NMOS transistor'"'"'s body is connected to ground, or the second PMOS transistor'"'"'s body is connected to V_DD, or both.

Claims

1. A semiconductor integrated circuit device comprising:

an input terminal which includes a first node;

an output which includes a second node;

a first NMOS transistor having a gate connected to the first node, a source connected to ground, a drain connected to the second node, and a body which includes a third node;

a second NMOS transistor having a gate connected to a power supply line, and a drain and source of which one is connected to the first node and the other is connected to the third node;

a first PMOS transistor having a gate connected to the first node, a source connected to the power supply line, a drain connected to the second node, and a body which includes a fourth node; and

a second PMOS transistor having a gate connected to ground, and a drain and source of which one is connected to the first node and the other is connected to the fourth node,

wherein the second NMOS transistor further has a body connected to ground.

2. A semiconductor integrated circuit device comprising:

an input terminal which includes a first node;

an output which includes a second node;

a first NMOS transistor having a gate connected to the first node, a source connected to ground, a drain connected to the second node, and a body which includes a third node;

a second NMOS transistor having a gate connected to a power supply line, and a drain and source of which one is connected to the first node and the other is connected to the third node;

a first PMOS transistor having a gate connected to the first node, a source connected to the power supply line, a drain connected to the second node, and a body which includes a fourth node; and

a second PMOS transistor having a gate connected to ground, and a drain and source of which one is connected to the first node and the other is connected to the fourth node,

wherein the second PMOS transistor further has a body connected to a supply voltage line.

3. A semiconductor integrated circuit device comprising:

an input terminal which includes a first node;

an output which includes a second node;

a first NMOS transistor having a gate connected to the first node, a source connected to ground, a drain connected to the second node, and a body which includes a third node;

a second NMOS transistor having a gate connected to a power supply line, and a drain and source of which one is connected to the first node and the other is connected to the third node;

a first PMOS transistor having a gate connected to the first node, a source connected to the power supply line, a drain connected to the second node, and a body which includes a fourth node; and

a second PMOS transistor having a gate connected to ground, and a drain and source of which one is connected to the first node and the other is connected to the fourth node,

wherein the second NMOS transistor further has a body connected to ground, and the second PMOS transistor further has a body connected to a supply voltage line.

4. A semiconductor integrated circuit device comprising:

an input terminal which includes a first node;

a ground line which includes a second node;

an output which includes a third node;

a power supply line which includes a fourth node;

a first NMOS transistor having a gate connected to the first node, a source connected to the second node, a drain connected to the third node, and a body which includes a fifth node; and

a second NMOS transistor having a gate connected to the fourth node, a drain and source of which one is connected to the first node and the other is connected to the fifth node, and a body which includes a sixth node,

wherein the sixth node is connected to ground.

5. A semiconductor integrated circuit device comprising:

an input terminal which includes a first node;

a ground line which includes a second node;

an output which includes a third node;

another ground line which includes a fourth node;

a first PMOS transistor having a gate connected to the first node, a source connected to the second node, a drain connected to the third node, and a body which includes a fifth node; and

a second PMOS transistor having a gate connected to the fourth node, a drain and source of which one is connected to the first node and the other is connected to the fifth node, and a body which includes a sixth node

wherein the sixth node is connected to a supply voltage line.