Aggregation of cache-updates in a multi-processor, shared-memory system
First Claim
1. A cache memory arrangement for a shared memory system including storage implemented on a plurality of intercoupled processing nodes, comprising at each node:
- a higher-level cache and a lower-level cache, wherein the higher and lower-level caches include respective pluralities of cache lines and the higher-level cache checks for presence of a requested address before conditionally presenting the requested address to the lower-level cache;
a coherence controller coupled to the higher and lower-level caches and to the storage elements, the coherence controller configured to maintain cache coherency for the higher-level cache consistent with an invalidation-based cache coherence protocol while maintaining cache coherency for the lower-level cache consistent with an update-based cache coherence protocol.
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Accused Products
Abstract
Method and arrangement for cache management in a shared memory system. Each of a plurality of intercoupled processing nodes includes a higher-level cache and a lower-level cache having corresponding cache lines. At each node, update-state information is maintained in association with cache lines in the higher-level cache. The update-state information for a cache line tracks whether there is pending update that needs to be distributed from the node. In response to a write-back operation referencing an address cached at a node, the node generates difference data that specifies differences between data in a cache line for the address in the higher-level cache and data in a corresponding cache line in the lower-level cache. The difference data are then provided to one or more other nodes with cached versions of the cache line for the address.
26 Citations
28 Claims
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1. A cache memory arrangement for a shared memory system including storage implemented on a plurality of intercoupled processing nodes, comprising at each node:
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a higher-level cache and a lower-level cache, wherein the higher and lower-level caches include respective pluralities of cache lines and the higher-level cache checks for presence of a requested address before conditionally presenting the requested address to the lower-level cache;
a coherence controller coupled to the higher and lower-level caches and to the storage elements, the coherence controller configured to maintain cache coherency for the higher-level cache consistent with an invalidation-based cache coherence protocol while maintaining cache coherency for the lower-level cache consistent with an update-based cache coherence protocol. - View Dependent Claims (2, 3, 4)
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5. A method for cache management in a shared memory system implemented on a plurality of intercoupled processing nodes, each processing node including a higher-level cache and a lower-level cache having corresponding cache lines, comprising:
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maintaining cache coherency for the higher-level cache consistent with an invalidation-based cache coherence protocol;
whilemaintaining cache coherency for the lower-level cache consistent with an update-based cache coherence protocol. - View Dependent Claims (6, 7)
in response to a write-back operation referencing an address cached at a node, generating difference data that specifies differences between data in a cache line for the address in the higher-level cache and data in a corresponding cache line in the lower-level cache; and
providing the difference data to one or more other nodes with cached versions of the cache line for the address.
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7. The method of claim 6, further comprising in response to receipt of the difference data at a node, purging a version of the cache line from the higher-level cache at the node and updating a version of the cache line in the lower-level cache at a node.
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8. An apparatus for cache management in a shared memory system implemented on a plurality of intercoupled processing nodes, each processing node including a higher-level cache and a lower-level cache having corresponding cache lines, comprising:
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means for maintaining cache coherency for the higher-level cache consistent with an invalidation-based cache coherence protocol;
whilemaintaining cache coherency for the lower-level cache consistent with an update-based cache coherence protocol.
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9. A cache memory arrangement for a shared memory system implemented on a plurality of intercoupled processing nodes, comprising at each node:
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a higher-level cache and a lower-level cache, wherein the higher and lower-level caches include respective pluralities of cache lines and the higher-level cache checks for presence of a requested address before conditionally presenting the requested address to the lower-level cache;
a plurality of storage elements for storage of update-state information of the cache lines in the higher-level cache;
a coherence controller coupled to the higher and lower-level caches and to the storage elements, the coherence controller configured to, generate a cache-line-fetch request with write permission for a requested address in a store operation if the requested address is not present in the lower-level cache, in response to data received for the cache-line-fetch request with write permission, store update-state information in one of the storage elements associated with the cache-line of the requested address, and in response to a write-back operation signal, clear the update-state information associated with the cache line, generate difference data that specifies differences between data in a cache line referenced by the cache-line code in the higher-level cache and data in a corresponding cache line in the lower-level cache, and provide the difference data to one more nodes with cached versions of the cache line. - View Dependent Claims (10, 11, 12)
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13. A cache memory arrangement for a shared memory system implemented on a plurality of intercoupled processing nodes, comprising at each node:
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a higher-level cache and a lower-level cache, wherein the higher and lower-level caches include respective pluralities of cache lines and the higher-level cache checks for presence of a requested address before conditionally presenting the requested address to the lower-level cache;
an update-pending queue, each entry in the update-pending queue identifying a cache line in the higher-level cache;
a coherence controller coupled to the higher and lower-level caches and to the update-pending queue, the coherence controller configured to, in response to a memory-write cache-line fetch request received from a requester processing node, the memory-write cache-line fetch request including a requested address, provide a cache line with the requested address to the requester node, in response to a receipt of a cache line with write permission for a requested address, enter a cache-line code that identifies the cache line of the requested address in the update-pending queue, in response to a write-back operation signal, remove a cache-line code from the update-pending queue, generate difference data that specifies differences between data in the higher-level cache for a cache line referenced by the cache-line code and a corresponding cache line in the lower-level cache, and provide the difference data to a home node that hosts the cache line, and in response to receipt of difference data, distribute the difference data to one or more nodes having cached versions of the associated cache line. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method for cache management in a shared memory system implemented on a plurality of intercoupled processing nodes, each processing node including a higher-level cache and a lower-level cache having corresponding cache lines, comprising:
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maintaining update-state information in association with cache lines in the higher-level cache, wherein the update-state information for a cache line indicates pending updates from the node with a cached version of the cache line;
in response to a write-back operation referencing an address cached at a node, generating difference data that specifies differences between data in a cache line for the address in the higher-level cache and data in a corresponding cache line in the lower-level cache; and
providing the difference data to one or more other nodes with cached versions of the cache line for the address. - View Dependent Claims (23, 24, 25, 26, 27)
in response to the write-back operation, removing from the update-pending queue the cache-line code associated with the cache line for the address.
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25. The method of claim 23, wherein the each memory address is hosted by a home node and further comprising:
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providing the difference data to the home node; and
distributing the difference data from the home node to the one or more other nodes.
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26. The method of claim 25, further comprising selecting at each node that hosts a range of memory addresses, an update-based or invalidation-based cache coherence protocol for each address requested with write permission, wherein the update-state information for a cache line indicates write permission at the node with a cached version of the cache line with update-based cache coherence protocol.
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27. The method of claim 26, further comprising maintaining at each node that hosts a range of memory addresses, a directory having entries that identify cache lines that are cached in the hosted range of addresses, read-write permissions associated with the cache lines, and cache coherence protocols associated with the cache lines.
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28. An apparatus for cache management in a shared memory system implemented on a plurality of intercoupled processing nodes, each processing node including a higher-level cache and a lower-level cache having corresponding cache lines, comprising:
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means for maintaining update-state information in association with cache lines in the higher-level cache, wherein the update-state information for a cache line indicates pending updates from the node with a cached version of the cache line;
means, responsive to a write-back operation referencing an address cached at a node, for generating difference data that specifies differences between data in a cache line for the address in the higher-level cache and data in a corresponding cache line in the lower-level cache; and
means for providing the difference data to one or more other nodes with cached versions of the cache line for the address.
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Specification