Controlled thickness gate stack

• US 6,680,516 B1
• Filed: 12/06/2002
• Issued: 01/20/2004
• Est. Priority Date: 12/06/2002
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Blosse, Alain, Ramkumar, Krishnaswamy
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/313,267
• Time in Patent Office: 410 Days
• Field of Search: 257/412, 257/413, 438/197
• US Class Current: 257/412
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence

Abstract

A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate,

a gate layer, on the semiconductor substrate,

a metallic layer, on the gate layer, and

an etch-stop layer, on the metallic layer,

wherein a distance between the substrate and a top of the etch-stop layer is a gate stack height,

the gate stack height is at most 2700 angstroms,

the etch-stop layer has a thickness of at least 800 angstroms,

the gate layer comprises a P⁺ region and an N⁺ region, and the P⁺ and N⁺ regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns, and

the etch-stop layer comprises nitride.

2. The semiconductor structure of claim 1, wherein the etch-stop layer has a thickness of at least 1100 angstroms.

3. The semiconductor structure of claim 1, wherein the metallic layer comprises tungsten.

4. An integrated circuit comprising a plurality of semiconductor structures of claim 1,

wherein the semiconductor structures further comprise a dielectric layer on the substrate, and a via contact through the dielectric layer to the substrate, and

wherein the average distance between the via contact and the gate layer in the plurality of semiconductor structures is at most one-half the minimum gate layer width.

7. The semiconductor structure of claim 3, wherein the etch stop layer comprises nitride.

8. The semiconductor structure of claim 7, wherein the etch stop layer has a thickness of at least 1100 angstroms.

9. The semiconductor structure of claim 7, wherein the gate layer comprises a P⁺ region and an N⁺ region, and

wherein the P⁺ and N⁺ regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns.

10. The semiconductor structure of claim 7, wherein the metallic layer comprises tungsten.

5. A semiconductor structure, comprising;

a semiconductor substrate,

a gate layer, on the semiconductor substrate,

a metallic layer, on the gate layer,

an etch-stop layer, on the metallic layer,

an insulating layer, on the etch-stop layer, and on the substrate, and

a via, through the insulating layer, on the substrate,

wherein an area of contact between the via and the substrate has a via width,

the via width is at most 0.12 micron,

a distance between the substrate and a top of the etch-stop layer has a gate stack height, and

the gate stack height is at most 2700 angstroms.

6. The semiconductor structure of claim 5, wherein the etch-stop layer has a thickness of at least 800 angstroms.

11. An integrated circuit comprising a plurality of semiconductor structures of claim 5, wherein the average distance between the via and the gate layer in the plurality of semiconductor structures is at most one-half the minimum gate layer width.

12. A method of making a semiconductor structure, comprising:

forming a gate layer, on a semiconductor substrate,

forming a metallic layer, on the gate layer, and

forming an etch-stop layer having a thickness of at least 1500 angstroms, on the metallic layer,

forming an insulating layer, on the etch-stop layer, and on the substrate, and

forming a via, through the insulating layer, to the substrate,

wherein a distance between the substrate and a top of the etch-stop layer is a gate stack height, and

the gate stack height is at most 2700 angstroms,

an area of contact between the via and the substrate has a via width,

the via width is at most 0.12 micron, and

the etch-stop layer has a thickness of at least 800 angstroms after forming the insulating layer, and

the etch stop layer comprises nitride.

13. The method of claim 12, wherein the forming of the etch-stop layer is forming the etch-stop layer having a thickness of at least 1800 angstroms.

14. The method of claim 12, wherein

the forming of the gate layer is forming the gate layer having a thickness of 400-1200 angstroms, and

the forming of the metallic layer is forming the metallic layer having a thickness of 200-600 angstroms.

15. A method of making a semiconductor device, comprising:

forming a semiconductor structure by the method of claim 12, and

forming a semiconductor device from the semiconductor structure.

16. A method of making an electronic device, comprising:

forming a semiconductor device by the method of claim 13, and

forming an electronic device comprising the semiconductor device.

17. An integrated circuit comprising a plurality of semiconductor structures, wherein the semiconductor structures comprise:

a semiconductor substrate,

a gate layer, on the semiconductor substrate,

a metallic layer, on the gate layer,

an etch-stop layer, on the metallic layer,

a dielectric layer on the substrate, and a via contact through the dielectric layer to the substrate,

wherein a distance between the substrate and a top of the etch-stop layer is a gate stack height,

the gate stack height is at most 2700 angstroms, and

the etch-stop layer has a thickness of at least 800 angstroms, and

the average distance between the via contact and the gate layer in the plurality of semiconductor structures is at most one-half the minimum gate layer width.

18. The integrated circuit of claim 17 wherein the etch-stop layer of the semiconductor structures comprises nitride.

19. The integrated circuit of claim 17 wherein the etch-stop layer of the semiconductor structures has a thickness of at least 1100 angstroms.

20. The integrated circuit of claim 17 wherein the metallic layer of the semiconductor structures comprises tungsten.