Controlled thickness gate stack

  • US 6,680,516 B1
  • Filed: 12/06/2002
  • Issued: 01/20/2004
  • Est. Priority Date: 12/06/2002
  • Status: Active Grant
First Claim
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1. A semiconductor structure, comprising:

  • a semiconductor substrate, a gate layer, on the semiconductor substrate, a metallic layer, on the gate layer, and an etch-stop layer, on the metallic layer, wherein a distance between the substrate and a top of the etch-stop layer is a gate stack height, the gate stack height is at most 2700 angstroms, the etch-stop layer has a thickness of at least 800 angstroms, the gate layer comprises a P+ region and an N+ region, and the P+ and N+ regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns, and the etch-stop layer comprises nitride.

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