Bus arbitration circuit responsive to latency of access requests and the state of the memory circuit

• US 6,684,302 B2
• Filed: 07/25/2002
• Issued: 01/27/2004
• Est. Priority Date: 01/19/1999
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Kershaw, Daniel
• Primary Examiner(s): Lane, Jack A.
• Application Number:
  US10/202,030
• Publication Number:
  US 20020188809A1
• Time in Patent Office: 551 Days
• Field of Search: 711/133, 711/151, 710/112, 710/116, 710/39, 710/41
• US Class Current: 711/151
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/127 using additional replacement algorithms
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold. A bus arbitration circuit 12 is provided that re-arbitrates bus master priorities in dependence upon determined latencies for respective memory access requests. As an example, if a high priority memory access request results a cache miss, with a lower priority memory access request resulting in a cache hit, then the lower priority memory access request will be re-arbitrated to be performed ahead of the normally higher priority memory access request and may be finished before that higher priority memory access request starts to return data words to a data bus 14.

Claims

1. Data processing apparatus comprising:

(i) a memory circuit;

(ii) a data bus coupled to said memory circuit;

(iii) a plurality of bus master circuits coupled to said data bus for issuing memory access requests to said memory circuit via said data bus;

(iv) a bus arbitration circuit for controlling in accordance with a hierarchy of bus master priorities which bus master is granted priority in gaining use of said data bus when more two or more bus masters issue temporally overlapping memory access requests;

wherein

(v) said bus arbitration circuit is responsive to a determination of latency of pending memory access requests calculated in dependence upon a current state of said memory circuit to re-arbitrate priority in gaining use of said data bus between bus masters such that a first bus master circuit having a first pending memory access request and a lower position in said hierarchy than a second bus master circuit having a second pending memory access request may gain use of said data bus ahead of said second bus master circuit if said first memory access request has a lower latency than said second memory access request.

2. Data processing apparatus as claimed in claim 1, wherein said first bus master circuit is given use of said data bus ahead of said second bus master circuit when said first memory access request has a latency such that it may be completed before said second memory access request is ready to transfer data words via said data bus.

3. Data processing apparatus as claimed in claim 1, wherein said memory circuit comprises a cache memory and a main memory.

4. Data processing apparatus as claimed in claim 3, wherein when said second memory access request results in a cache miss so that a main memory access is required, said bus arbitration circuit re-arbitrates priority such that if said second memory access request results in a cache miss, then said first bus master circuit will gain use of said data bus ahead of said first bus master circuit.

5. Data processing apparatus as claimed in claim 1, wherein said memory circuit comprises a plurality of main memory units, said plurality of main memory units being operable to independently and concurrently service respective memory access requests.

6. Data processing apparatus as claimed in claim 5, wherein, if said second memory access request is to a main memory unit that is already busy servicing another memory access request and said second memory access request is to a main memory unit that is not already busy servicing a memory access request such that said second memory access request has a lower latency than said first memory access request, then said bus arbitration circuit re-arbitrates between said plurality of bus master circuits such that said second bus master circuit gains use of said data bus ahead of said first bus master circuit.

7. Data processing apparatus as claimed in claim 5, wherein said plurality of main memory units are a plurality of banks of dynamic random access memory.

8. Data processing apparatus as claimed in claim 1, wherein said memory circuit, said data bus, said plurality of bus master circuits and said bus arbitration circuit are provided together on an integrated circuit.

9. Data processing apparatus as claimed in claim 1, wherein said plurality of bus master circuits include a central processing unit.

10. Data processing apparatus as claimed in claim 1, wherein said plurality of bus master circuits include a video display driving circuit.

11. A data processing method comprising the steps of:

(i) issuing memory access requests from a plurality of bus master circuits to a memory circuit via a data bus;

(ii) controlling, in accordance with a hierarchy of bus master priorities, which bus master is granted priority in gaining use of said data bus when more two or more bus masters issue temporally overlapping memory access requests;

wherein (iii) in response to a determination of latency of pending memory access requests calculated in dependence upon a current state of said memory circuit, priority in gaining use of said data bus between bus masters is re-arbitrated such that a first bus master circuit having a first pending memory access request and a lower position in said hierarchy than a second bus master circuit having a second pending memory access request may gain use of said data bus ahead of said second bus master circuit if said first memory access request has a lower latency than said second memory access request.

12. Data processing apparatus comprising:

(i) a memory circuit;

(ii) a data bus coupled to said memory circuit;

(iii) a plurality of bus master circuits coupled to said data bus for issuing memory access requests to said memory circuit via said data bus;

(iv) a bus arbitration circuit for controlling in accordance with a hierarchy of bus master priorities which bus master is granted priority in gaining use of said data bus when two or more bus masters issue temporally overlapping memory access requests;

wherein

(v) said bus arbitration circuit is responsive to a determination of latency of pending memory access requests calculated in dependence upon a current state of said memory circuit to re-arbitrate priority in gaining use of said data bus between bus masters such that a first bus master circuit having a first pending memory access request and a lower position in said hierarchy than a second bus master circuit having a second pending memory access request may gain use of said data bus ahead of said second bus master circuit if said first memory access request has a lower latency than said second memory access request;

wherein said first bus master circuit is given use of said data bus ahead of said second bus master circuit when said first memory access request has a latency such that it may be completed before said second memory access request is ready to transfer data words via said data bus.

13. A data processing method comprising the steps of:

(i) issuing memory access requests from a plurality of bus master circuits to a memory circuit via a data bus;

(ii) controlling, in accordance with a hierarchy of bus master priorities, which bus master is granted priority in gaining use of said data bus when two or more bus masters issue temporally overlapping memory access requests;

wherein

(iii) in response to a determination of latency of pending memory access requests calculated in dependence upon a current state of said memory circuit, priority in gaining use of said data bus between bus masters is re-arbitrated such that a first bus master circuit having a first pending memory access request and a lower position in said hierarchy than a second bus master circuit having a second pending memory access request may gain use of said data bus ahead of said second bus master circuit if said first memory access request has a lower latency than said second memory access request; and

(iv) giving said first bus master circuit use of said data bus ahead of said second bus master circuit when said first memory access request has a latency such that it may be completed before said second memory access request is ready to transfer data words via said data bus.