Defect detection in semiconductor devices

• US 6,686,757 B1
• Filed: 09/30/1999
• Issued: 02/03/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Birdsley, Jeffrey D., Davis, Brennan V., Ring, Rosalinda M., Goruganthu, Rama R., Bruce, Michael R.
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US09/409,217
• Time in Patent Office: 1,587 Days
• Field of Search: 324/750, 324/751, 324/752, 324/501, 324/755, 324/765, 736/32, 736/43
• US Class Current: 324/754.22
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

Claims

1. A method for testing an integrated circuit, wherein the circuit has circuitry in a circuit side opposite a back side, the method comprising:

removing substrate from the back side and exposing a target region;

applying an energy source at the target region, thereby generating a plurality response signals from the integrated circuit;

detecting the response signals from in the integrated circuit via at least one detector;

correlating the detected response signals with a reference signal to determine the amount of deviation from the reference signal; and

identifying the type of defect in the circuit as a function of the deviation between the detected response signals and the reference signal and as function of the energy source used to generate the response signal.

2. The method for testing an integrated circuit according to claim 1, wherein applying an energy source at the target region includes using a passive source that includes at least one of nIR, sonic and ultrasonic energy.

3. The method for testing an integrated circuit according to claim 1, wherein applying an energy source at the target region includes using a source that generates acoustic signals due to the internal vibrations within the circuit, the source including at least one of a laser and a heat generating device.

4. The method for testing an integrated circuit according to claim 1, wherein applying an energy source includes using at least one of:

an ion beam, an electron beam and an x-ray beam.

5. The method for testing an integrated circuit according to claim 1, wherein the energy source is synchronized with the at least one detector, and wherein identifying the type of defect includes detecting the shift of the correlated detected signal versus the reference signal.

6. The method for testing an integrated circuit according to claim 1, wherein correlating the detected response signal to a reference signal includes using a computer arrangement.

7. The method for testing an integrated circuit according to claim 1, wherein identifying the type of defect in the circuit as a function of the defined deviation between the response signal and the reference signal identifying at least one of:

an open circuit, a short circuit, a partial open and a microvoid.

8. The method for testing an integrated circuit according to claim 1, wherein identifying at least one defect in the circuit as a function of the defined deviation between the response signal and the reference signal includes comparing the correlated detected signal to a reference signal for a non-defective integrated circuit.

9. The method for testing an integrated circuit, according to claim 1, wherein the integrated circuit is not powered.

10. The method for testing an integrated circuit, according to claim 8, wherein removing substrate from the back side and exposing a target region includes removing an amount of substrate that corresponds to an amount of substrate removed from the non-defective integrated circuit when the reference parameter was ascertained.

11. A system for testing an integrated circuit having circuitry in a circuit side opposite a back side, the system comprising:

means for removing substrate from the back side;

an energy source adapted to generate response signals that is emitted from the integrated circuit;

means for detecting the response signals emitted from the integrated circuit;

means for correlating the detected response signals with a reference signal to determine the amount of deviation from the reference signal that has occurred; and

means for identifying the type of defect in the circuit as a function of the deviation and the energy source used to generate the response signals.

12. A system for testing an integrated circuit having circuitry in a circuit side opposite a back side, the system comprising:

a substrate removal device;

an energy source configured and arranged to excite circuitry in the integrated circuit;

a plurality of energy source detectors; and

a computer arrangement configured to correlate detected response signals with a reference signal to determine the amount of deviation between signals, and to identify the type of defect in the circuit as a function of the signal deviations and as function of the energy source used to generate the response signal.

13. The system for testing an integrated circuit, according to claim 12, wherein the energy source, the at least one energy source detector, and the computer are communicatively coupled.

14. The system for testing an integrated circuit, according to claim 13, wherein the computer is configured and arranged to control the energy source.

15. A system for testing an integrated circuit, according to claim 12, wherein the computer is further configured and arranged to detect at least one defect in the integrated circuit using the correlated detected response signals.

16. A system for testing an integrated circuit according to claim 15, wherein the computer is configured and arranged to detect at least one of:

a short circuit, an open circuit, a partial open circuit and a microvoid.