Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor

• US 6,686,803 B1
• Filed: 07/10/2001
• Issued: 02/03/2004
• Est. Priority Date: 07/10/2000
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Baird, Rex T., Perrott, Michael H., Hein, Jerrell P.
• Primary Examiner(s): Tokar; Michael
• Assistant Examiner(s): Mai; Lam T.
• Application Number:
  US09/902,543
• Time in Patent Office: 938 Days
• Field of Search: 331/10,117 R 330/107 333/173
• US Class Current: 331/10
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device. Moreover, if one of the available reference clock frequencies is chosen to correspond to an internal test mode, the device may be placed in a test mode without requiring any additional dedicated input pins for that purpose, either.

Claims

1. An integrated circuit comprising:

a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies, said signal generation circuit for generating an output signal related to the frequency reference signal; and

a frequency detection circuit responsive to the externally provided frequency reference signal, for determining which of the at least two possible reference frequencies is present, and for generating a control signal accordingly.

2. The integrated circuit as recited in claim 1 wherein the output signal comprises a periodic signal having a nominal frequency related to the externally provided frequency reference signal.

3. The integrated circuit as recited in claim 1 wherein the frequency detection circuit is configured to determine, absent any additional externally provided signal to so indicate, which of the at least two possible reference frequencies is present.

4. The integrated circuit as recited in claim 1 wherein the frequency reference signal is provided by an externally generated reference clock signal.

5. The integrated circuit as recited in claim 1 wherein the frequency reference signal is provided by a resonant circuit coupled to the integrated circuit.

6. The integrated circuit as recited in claim 1 wherein:

when the reference frequency signal is provided with a frequency substantially equal to a first reference frequency, the signal generation circuit is configured to generate the output signal with a nominal frequency which is a first multiple of the reference frequency signal; and

when the reference frequency signal is provided with a frequency substantially equal to a second reference frequency, the signal generation circuit is configured to generate the output signal with a nominal frequency which is a second multiple of the reference frequency signal.

7. The integrated circuit as recited in claim 6 wherein:

the nominal frequency of the output signal, when generated as the first multiple of the first reference frequency, and when generated as the second multiple of the second reference frequency, is substantially identical.

8. The integrated circuit as recited in claim 6 wherein:

the value of the first multiple comprises a first integer; and

the value of the second multiple comprises a second integer different from the first integer.

9. The integrated circuit as recited in claim 6 wherein:

the value of the first multiple comprises a first ratio of integers; and

the value of the second multiple comprises a second ratio of integers different from the first ratio.

10. The integrated circuit as recited in claim 6 wherein:

the value of the first multiple and the value of the second multiple are identical.

11. The integrated circuit as recited in claim 2 wherein the output signal comprises a VCO output clock signal.

12. An integrated circuit comprising:

a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said signal generation circuit for generating a periodic output signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal; and

a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the periodic output signal accordingly.

13. The integrated circuit as recited in claim 12 wherein the frequency reference signal is provided by an externally generated reference clock signal.

14. The integrated circuit as recited in claim 12 wherein the frequency reference signal is provided by a resonant circuit coupled to the integrated circuit.

15. The integrated circuit as recited in claim 12 wherein:

the multiple by which the nominal frequency of the output signal relates to the frequency of the externally provided reference frequency signal is identical for at least two of the possible reference frequencies of the externally provided frequency reference signal.

16. The integrated circuit as recited in claim 15 wherein:

the multiple by which the nominal frequency of the output signal relates to the frequency of the externally provided reference frequency signal is different for at least two of the possible reference frequencies of the externally provided frequency reference signal.

17. The integrated circuit as recited in claim 16 wherein:

the nominal frequency of the output signal is substantially identical for at least two of the possible reference frequencies of the externally provided frequency reference signal.

18. The integrated circuit as recited in claim 15 wherein:

the multiple by which the nominal frequency of the output signal relates to the frequency of the externally provided reference frequency signal is different for each of the possible reference frequencies of the externally provided frequency reference signal; and

the nominal frequency of the output signal is substantially identical for each of the possible reference frequencies of the externally provided frequency reference signal.

19. The integrated circuit as recited in claim 12 wherein:

the multiple by which the nominal frequency of the output signal relates to the frequency of the externally provided reference frequency signal, for at least one of the possible reference frequencies of the externally provided frequency reference signal, comprises a ratio of integers.

20. The integrated circuit as recited in claim 12 wherein:

the multiple by which the nominal frequency of the output signal relates to the frequency of the externally provided reference frequency signal, for at least one of the possible reference frequencies of the externally provided frequency reference signal, comprises an integer.

21. An integrated circuit comprising:

a signal generation circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said signal generation circuit for generating a periodic output signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal; and

circuit means for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the periodic output signal accordingly.

22. The integrated circuit as recited in claim 21 wherein the frequency reference signal is provided by an externally generated reference clock signal.

23. The integrated circuit as recited in claim 21 wherein the frequency reference signal is provided by a resonant circuit coupled to the integrated circuit.

24. The integrated circuit as recited in claim 21 wherein the circuit means comprises:

phase locked loop circuit means having a capture range, when expressed as a percentage of its nominal free-running frequency, which is less than the proportion by which the possible reference frequencies that are closest in frequency differ.

25. The integrated circuit as recited in claim 24 wherein the circuit means comprises:

first means for generating a first signal related to the externally provided frequency reference signal;

second means for generating a second signal related to the output signal of the signal generation circuit;

third means for determining the number of cycles of one of the first or second signals which occur during a portion of the period of the other of the first or second signals.

26. An integrated circuit comprising:

a phase locked loop circuit having an input for receiving an externally provided reference clock signal having a frequency substantially equal to any of at least two possible reference frequencies, and for generating a VCO output signal having a nominal frequency related to that of the reference clock signal; and

a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the at least two possible reference clock frequencies is present, and for communicating an indication thereof to the phase locked loop circuit.

27. The integrated circuit device as recited in claim 26 wherein the frequency detection circuit comprises:

a second phase locked loop circuit having a capture range, when expressed as a percentage of its nominal free-running frequency, which is less than the proportion by which the possible reference frequencies that are closest in frequency differ.

28. The integrated circuit device as recited in claim 26 wherein:

at least one of the possible reference clock frequencies corresponds to a normal operating mode of the device; and

at least one of the possible reference clock frequencies corresponds to a test mode of the device.

29. In an integrated circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies, said integrated circuit requiring a different internal configuration depending upon which reference frequency is provided, a method of eliminating at least one external pin otherwise required to convey to the integrated circuit an external signal for indicating which reference frequency is provided, said method comprising the steps of:

generating on the integrated circuit a first signal having a frequency within a predetermined range;

comparing the externally provided frequency reference signal to the first signal, to determine which reference frequency is provided;

generating at least one control signal as a result of the comparing step to indicate which reference frequency is provided; and

configuring the integrated circuit in accordance with the at least one control signal.

30. The method as recited in claim 29 wherein the comparing step comprises the steps of:

generating a second signal having a nominal frequency which is a selectable fraction of the first signal;

stepping through each selectable fraction and comparing the resulting second signal to a third signal related to the frequency reference signal, until a selected fraction is found that generates a nominal frequency of the second signal which is within a chosen tolerance of the frequency of the third signal; and

then

inferring the frequency of the frequency reference signal in accordance with the selected fraction, the relationship of the third signal to the frequency reference signal, and the nominal frequency of the first signal.

31. The method as recited in claim 29 wherein the comparing step comprises the steps of:

a second signal having a nominal frequency which is a selectable fraction of the frequency reference signal;

stepping through each selectable fraction and comparing the resulting second signal to a third signal related to the first signal, until a selected fraction is found that generates a nominal frequency of the second internal signal which is within a chosen tolerance of the frequency of the third signal; and

then

inferring the frequency of the frequency reference signal in accordance with the selected fraction, the relationship of the third signal to the first signal, and the nominal frequency of the first signal.

32. In an integrated circuit responsive to an externally provided frequency reference signal having a frequency substantially equal to any of at least two possible reference frequencies, a method of determining which reference frequency is provided comprising of:

generating on the integrated circuit a first signal having a nominal frequency within a predetermined range;

comparing each of a plurality of signals having a respective frequency related to the externally provided frequency reference signal to the first signal, to determine which of the plurality of signals most closely matches the frequency of the first signal;

inferring the frequency of the frequency reference signal in accordance with relationship between the signal that most closely matches the frequency of the first signal and the externally provided frequency reference signal, and the nominal frequency of the first signal.

33. In a system including an integrated circuit responsive to an externally provided frequency reference signal, said integrated circuit having at least two possible modes of operation, a method of communicating a selected mode of operation to the integrated circuit, said method comprising the steps of:

providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a first reference frequency to select a first mode of operation; and

providing to the integrated circuit an external frequency reference signal with a frequency substantially equal to a second reference frequency to select a second mode of operation.

34. The method as recited in claim 33 wherein:

the first mode of operation is a normal operating mode; and

the second mode of operation is a test mode.

35. The method as recited in claim 33 wherein:

the first and second modes of operation are both normal operating modes.

36. An integrated circuit for recovering separate clock and data signals from an incoming bit-serial clock-encoded data input stream comprising:

a phase locked loop circuit responsive to the incoming bit-serial clock-encoded data input stream and further responsive to an externally provided frequency reference signal having a frequency substantially equal to any of a plurality of possible reference frequencies, said phase locked loop circuit including a voltage controlled oscillator (VCO) circuit for generating a VCO output clock signal having a nominal frequency that is a configurable multiple of the frequency of the externally provided frequency reference signal; and

a frequency detection circuit for determining, absent any additional externally provided signal to so indicate, which of the plurality of possible reference frequencies is present, and for configuring the multiple for the VCO output clock signal accordingly.

37. The integrated circuit as recited in claim 36 wherein the bit-serial clock-encoded data input stream comprises a SONET data stream.

38. The integrated circuit as recited in claim 36 wherein the frequency reference signal is provided by an externally generated reference clock signal.

39. The integrated circuit as recited in claim 36 wherein the frequency reference signal is provided by a resonant circuit coupled to the integrated circuit.

40. The integrated circuit as recited in claim 36 wherein:

the multiple by which the nominal frequency of the VCO output clock signal relates to the frequency of the externally provided reference frequency signal is different for at least two of the possible reference frequencies of the externally provided frequency reference signal; and

the nominal frequency of the VCO output clock signal is substantially identical for at least two of the possible reference frequencies of the externally provided frequency reference signal.

41. The integrated circuit as recited in claim 36 wherein:

at least one of the possible reference frequencies of the externally provided frequency reference signal corresponds to a normal operating mode of the integrated circuit; and

at least one of the possible reference frequencies of the externally provided frequency reference signal corresponds to a test mode of the integrated circuit.

42. The integrated circuit as recited in claim 41 wherein:

at least two of the possible reference frequencies of the externally provided frequency reference signal each corresponds to a respective normal operating mode of the integrated circuit; and

at least two of the possible reference frequencies of the externally provided frequency reference signal each corresponds to a respective test mode of the integrated circuit.

43. The integrated circuit as recited in claim 36 wherein each of the possible reference frequencies is chosen from a group of frequencies in which each respective frequency of the group relates to its next lower frequency of the group, if such exists, and its next higher frequency of the group, if such exists, by a fixed proportion.

44. The integrated circuit as recited in claim 43 wherein the fixed proportion comprises a factor of 2.

45. The integrated circuit as recited in claim 36 wherein the possible reference frequencies include approximately 155.52 MHz, approximately 77.76 MHz, and approximately 19.44 MHz.

46. The integrated circuit as recited in claim 43 wherein the possible reference frequencies further include approximately 38.88 MHz, approximately 9.72 MHz, and approximately 4.86 MHz.

47. The integrated circuit as recited in claim 46 wherein the possible reference frequencies of approximately 38.88 MHz, approximately 9.72 MHz, and approximately 4.86 MHz each correspond to a respective test mode of the integrated circuit.