Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations

• US 6,690,192 B1
• Filed: 10/16/2002
• Issued: 02/10/2004
• Est. Priority Date: 10/16/2002
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Wing, Choy Kwok
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US10/065,420
• Time in Patent Office: 482 Days
• Field of Search: 326/31-34, 326/26-27, 326/83, 326/86, 327/170, 327/108, 327/380, 327/381, 327/362, 327/378
• US Class Current: 326/32
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

Edge rates for output driver transistors are increased for slower conditions such as caused by supply-voltage, temperature, and process variations. The edge rates are increased by increasing charging and discharging currents to the gates of the driver transistors. Process-sensing transistors have gates tied to power or ground. Current through the process-sensing transistors changes with supply-voltage, temperature, and process variations. The currents through process-sensing transistors are used to generate process-compensated voltages that bias current sources and sinks to adjust process-dependent currents. Process-independent or fixed current sources and sinks use process-independent reference voltages ultimately generated from reference currents that are not sensitive to process variations. The process-dependent-currents are subtracted from the fixed currents to produce the charging and discharging currents.

Claims

1. A process-compensated output buffer comprising:

a reference voltage generator, receiving a reference current having substantially no process dependency, for generating p-channel reference voltages and n-channel reference voltages having substantially little process dependency;

a PMOS process compensator, receiving the p-channel reference voltages from the reference voltage generator, for generating a first control voltage between a;

frost fixed current source that receives the p-channel reference voltages and a frost process-compensated current sink;

a first control transistor for adjusting discharge current from a p-driver gate in response to the first control voltage;

an NMOS process compensator for generating process-compensated voltages that have a substantial process dependency;

an NMOS edge-rate increaser, receiving the n-channel reference voltages from the reference voltage generator and the process-compensated voltages from the NMOS process compensator, for generating a second control voltage between a fixed current sink that receives the n-channel reference voltages and a process-compensated current source that receives the process-compensated voltages; and

a second control transistor for adjusting charge current to an n-driver gate in response to the second control voltage,

whereby charge and discharge currents of driver gates are process-compensated.

2. The process-compensated output buffer of claim 1 further comprising:

an NMOS positive compensator, receiving the p-channel reference voltages from the reference voltage generator and the process-compensated voltages from the NMOS process compensator, for generating a third control voltage between a second fixed current source that receives the p-channel reference voltages and a second process-compensated current sink that receives the process-compensated voltages; and

a third control transistor for also adjusting charge current to the n-driver gate in response to the third control voltage;

whereby charge current is adjusted by both the second and third control voltages.

3. The process-compensated output buffer of claim 2 further comprising:

an NMOS edge-rate decreaser, coupled to adjust the second control voltage from the NMOS edge-rate increaser, receiving the p-channel reference voltages from the reference voltage generator and the process-compensated voltages from the NMOS process compensator, for generating an inverted voltage between a third fixed current source that receives the p-channel reference voltages and a third process-compensated current sink that receives the process-compensated voltages; and

inverting means, receiving the inverted voltage from the NMOS edge-rate decreaser, for inverting adjustments to the inverted voltage to adjust the second control voltage.

4. The process-compensated output buffer of claim 3 further comprising:

a PMOS positive compensator receiving the p-channel reference voltages from the reference voltage generator and receiving process-compensated voltages from the PMOS process compensator, for generating a second inverted voltage between a fourth fixed current source that receives the p-channel reference voltages and a fourth process-compensated current sink that receives the process-compensated voltages from the PMOS process compensator; and

second inverting means, receiving the inverted voltage from the PMOS positive compensator, for inverting adjustments to the second inverted voltage to adjust the second control voltage.

5. The process-compensated output buffer of claim 4 wherein the NMOS edge-rate increaser comprises:

a first p-channel transistor having a gate receiving a first process-compensated voltage;

a second p-channel transistor, having a gate receiving a second process-compensated voltage;

a first n-channel transistor having a gate receiving a first n-channel reference voltage;

a second n-channel transistor having a gate receiving a second n-channel reference voltage;

wherein the first p-channel transistor, the second p-channel transistor, the first n-channel transistor, and the second n-channel transistor are in series; and

a first p-channel mirror transistor having a gate and a drain connected together and to the second control voltage and to drains of the first p-channel transistor and the first n-channel transistor.

6. The process-compensated output buffer of claim 5 wherein the NMOS edge-rate decreaser comprises:

a third p-channel transistor having a gate receiving a first p-channel reference voltage;

a fourth p-channel transistor, having a gate receiving a second p-channel reference voltage;

a third n-channel transistor having a gate receiving a third process-compensated voltage;

a fourth n-channel transistor having a gate receiving a fourth process-compensated voltage;

wherein the third p-channel transistor, the fourth p-channel transistor, the third n-channel transistor, and the fourth n-channel transistor are in series;

a second mirror n-channel transistor, having a gate and a drain connected together and to drains of the third p-channel transistor and the third n-channel transistor; and

a first inverting n-channel transistor, having a gate connected to drains of the third p-channel transistor and the third n-channel transistor and having a drain connected to the second control voltage.

7. The process-compensated output buffer of claim 6 wherein the NMOS positive compensator comprises:

a fifth p-channel transistor having a gate receiving the first p-channel reference voltage;

a sixth p-channel transistor, having a gate receiving the second p-channel reference voltage;

a fifth n-channel transistor having a gate receiving a third n-channel reference voltage;

a sixth n-channel transistor having a gate receiving a fourth n-channel reference voltage;

wherein the fifth p-channel transistor, the sixth p-channel transistor, the fifth n-channel transistor, and the sixth n-channel transistor are in series;

a second inverting n-channel transistor, having a gate connected to drains of the fifth p-channel transistor and the fifth n-channel transistor and having a drain connected to the third control voltage; and

a third p-channel mirror transistor having a gate and a drain connected together and to the third control voltage and to a drain of the second inverting n-channel transistor.

8. The process-compensated output buffer of claim 7 wherein the reference voltage generator comprises:

a first reference n-channel transistor, receiving a first reference current at a drain, having a gate and the drain connected together as a first n-channel reference voltage;

a second reference n-channel transistor, receiving a second reference current at a drain, having a gate driven by the first n-channel reference voltage; and

a third reference n-channel transistor, in series with the second reference n-channel transistor, having a gate connected to the drain of the second reference n-channel transistor as a second n-channel reference voltage.

9. A buffer having internal currents compensated for supply-voltage, temperature, and process variations comprising:

a pull-up driver transistor for driving pull-up current to an output in response to a first gate;

a pull-down driver transistor for sinking pull-down current from the output in response to a second gate;

a first control transistor for controlling current to the first gate in response to a first control voltage;

a second control transistor for controlling current to the second gate in response to a second control voltage;

a first fixed current source for producing a first fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;

a first variable current sink for sinking a first variable current that is more sensitive to supply-voltage, temperature, and process variations than is the first fixed current;

a first mirror transistor, coupled to receive a first current difference, for generating the first control voltage in response to the first current difference, the first current difference being a difference between the first fixed current and the first variable current;

a second fixed current sink for sinking a second fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;

a second variable current source for producing a second variable current that is more sensitive to supply-voltage, temperature, and process variations than is the second fixed current; and

a second mirror transistor, coupled to supply a second current difference, for generating the second control voltage in response to the second current difference, the second current difference being a difference between the second variable current and the second fixed current,

whereby current differences between fixed and process-variable current sources control currents to gates of driver transistors.

10. The buffer of claim 9 further comprising:

a first data transistor in series with the first control transistor, the first data transistor being switched on and off to pass or block current from the first control transistor in response to input data;

a second data transistor in series with the second control transistor, the second data transistor being switched on and off to pass or block current from the second control transistor in response to input data.

11. The buffer of claim 10 wherein the pull-up driver transistor is a p-channel transistor;

wherein the first control transistor and the first data transistor and the first mirror transistor are each an n-channel transistor;

wherein the pull-down driver transistor is an n-channel transistor;

wherein the second control transistor and the second data transistor and the second mirror transistor are each a p-channel transistor.

12. The buffer of claim 11 wherein the first fixed current source comprises a p-channel transistor having a gate driven by a reference voltage that is relatively insensitive to supply-voltage, temperature, and process variations;

wherein the first variable current sink comprises an n-channel transistor having a gate driven by a process-compensated voltage that is relatively sensitive to supply-voltage, temperature, and process variations;

wherein the second fixed current sink comprises an n-channel transistor having a gate driven by a reference voltage that is relatively insensitive to supply-voltage, temperature, and process variations;

wherein the second variable current source comprises a p-channel transistor having a gate driven by a process-compensated voltage that is relatively sensitive to supply-voltage, temperature, and process variations.

13. The buffer of claim 11 wherein the first fixed current source comprises a of p-channel transistors in series having gates driven by reference voltages that are relatively insensitive to supply-voltage, temperature, and process variations;

wherein the first variable current sink comprises a pair of n-channel transistors in series having gates driven by process-compensated voltages that are relatively sensitive to supply-voltage, temperature, and process variations;

wherein the second fixed current sink comprises a pair of n-channel transistors in series having gates driven by reference voltages that are relatively insensitive to supply-voltage, temperature, and process variations;

wherein the second variable current source comprises a pair of p-channel transistors in series having gates driven by process-compensated voltages that are relatively sensitive to supply-voltage, temperature, and process variations.

14. The buffer of claim 13 wherein reference voltages are generated by a band-gap reference while process-compensated voltages are generated by drain voltages of transistors in series with other transistors.

15. The buffer of claim 14 further comprising:

a third control transistor for controlling current to the first gate in response to a third control voltage;

a fourth control transistor for controlling current to the second gate in response to a fourth control voltage;

a third fixed current source for producing a third fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;

a third variable current sink for sinking a third variable current that is more sensitive to supply-voltage, temperature, and process variations than is the third fixed current;

a third mirror transistor, coupled to receive a third current difference, for generating the third control voltage in response to the third current difference, the third current difference being a difference between the third fixed current and the third variable current;

a fourth fixed current sink for sinking a fourth fixed current that is relatively insensitive to supply-voltage, temperature, and process variations;

a fourth variable current source for producing a fourth variable current that is more sensitive to supply-voltage, temperature, and process variations than is the fourth fixed current; and

a fourth mirror transistor, coupled to supply a fourth current difference, for generating the fourth control voltage in response to the fourth current difference, the fourth current difference being a difference between the fourth variable current and the fourth fixed current.

16. The buffer of claim 15 wherein the first and third control transistors are in parallel to each other;

wherein the second and fourth control transistors are in parallel to each other,

whereby control currents are summed.

17. The buffer of claim 16 further comprising:

a first multiplexer, coupled between the first data transistor and the first gate of the pull-up driver transistor, the first multiplexer having an input connected to a power-supply for disabling the first gate; and

a second multiplexer, coupled between the second data transistor and the second gate of the pull-down driver transistor, the second multiplexer having an input connected to a ground for disabling the second gate,

whereby multiplexers switch discharge currents to disable driver transistors.

18. A compensated output buffer comprising:

reference voltage generator means, receiving a reference current having substantially no process dependency, for generating p-channel reference voltages and n-channel reference voltages having substantially little process dependency;

PMOS process compensator means, receiving the p-channel reference voltages from the reference voltage generator means, for generating a first control voltage between a fixed current source that receives the p-channel reference voltages and a compensated current sink;

first control transistor means for adjusting discharge current from a p-driver gate in response to the first control voltage;

NMOS process compensator means for generating compensated voltages that have a substantial process dependency;

NMOS edge-rate adjust means, receiving the n-channel reference voltages from the reference voltage generator means and the compensated voltages from the NMOS process compensator means, for generating a second control voltage between a fixed current sink that receives the n-channel reference voltages and a compensated current source that receives the compensated voltages; and

second control transistor means for adjusting charge current to an n-driver gate in response to the second control voltage,

whereby charge and discharge currents of driver gates are compensated.

19. The compensated output buffer of claim 18 further comprising:

NMOS second compensator means, receiving the p-channel reference voltages from the reference voltage generator means and the compensated voltages from the NMOS process compensator means, for generating a third control voltage between a fixed current source that receives the p-channel reference voltages and a compensated current sink that receives the compensated voltages; and

third control transistor means for adjusting charge current to the n-driver gate in response to the third control voltage;

whereby charge current is adjusted by both the second and third control voltages.

20. The compensated output buffer of claim 19 further comprising:

NMOS edge-rate re-adjust means, coupled to adjust the second control voltage from the NMOS edge-rate adjust means, receiving the p-channel reference voltages from the reference voltage generator means and the compensated voltages from the NMOS process compensator means, for generating an inverted voltage between a fixed current source that receives the p-channel reference voltages and a compensated current sink that receives the compensated voltages; and

inverting means, receiving the inverted voltage from the NMOS edge-rate re-adjust means, for inverting adjustments to the inverted voltage to adjust the second control voltage.