Dynamic queuing system incorporating multiple queues sharing a single memory
First Claim
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1. A dynamic quieting system for dynamically establishing a plurality of transmit and receive queues, comprising:
- a queue memory adapted to be dynamically shared by a plurality of transmit and receive queues, said queue memory divided into a plurality of equal length memory blocks;
a first linked list adapted to track memory blocks currently not used and available for use in a queue;
a plurality of queues, each said queue represented by a second linked list of one or more memory blocks of said queue memory, wherein a queue is created by allocating an available memory block from said queue memory, removing said allocated memory block from said first linked list and creating said second linked list for representing the one or more memory block that make up said queue;
a queue control circuit including;
means for writing to a queue including a write pointer for identifying the next location in a queue available for writing;
means for reading from a queue including read pointer for identifying the next location in a queue to be read;
means for increasing the size of a queue when a queue becomes full, including allocating an additional memory block from said queue memory, removing the allocated memo block from the first linked list and adding the newly allocated memory block to the second linked list; and
means for reducing the size of a queue when a memory block becomes empty, including de-allocating the empty memory block, adding the de-allocated memory block to the first linked list and removing the de-allocated memory block from the second linked list.
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Abstract
A dynamic queuing system wherein a single memory is shared among a plurality of different queues. A single memory, termed a queue memory, is by ally shared by one or more queue. The queue memory is divided into a plurality of memory blocks that we initially empty. An empty list functions to track which memory blocks are empty and available for use in a queue. Each queue constructed utilizes one or more memory blocks. When a queue becomes full, an additional memory block is allocated to it. Conversely, as memory blocks of a queue are read, i.e. emptied, they are returned to the pool of empty memory blocks for use by other queued.
37 Citations
27 Claims
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1. A dynamic quieting system for dynamically establishing a plurality of transmit and receive queues, comprising:
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a queue memory adapted to be dynamically shared by a plurality of transmit and receive queues, said queue memory divided into a plurality of equal length memory blocks;
a first linked list adapted to track memory blocks currently not used and available for use in a queue;
a plurality of queues, each said queue represented by a second linked list of one or more memory blocks of said queue memory, wherein a queue is created by allocating an available memory block from said queue memory, removing said allocated memory block from said first linked list and creating said second linked list for representing the one or more memory block that make up said queue;
a queue control circuit including;
means for writing to a queue including a write pointer for identifying the next location in a queue available for writing;
means for reading from a queue including read pointer for identifying the next location in a queue to be read;
means for increasing the size of a queue when a queue becomes full, including allocating an additional memory block from said queue memory, removing the allocated memo block from the first linked list and adding the newly allocated memory block to the second linked list; and
means for reducing the size of a queue when a memory block becomes empty, including de-allocating the empty memory block, adding the de-allocated memory block to the first linked list and removing the de-allocated memory block from the second linked list. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A dynamic queuing method for dynamically establishing a plurality of transit and receive queues, said method comprising the steps of:
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dividing a queue memory into a plurality of equal length memory blocks, said queue memory adapted to be dynamically shared by a plurality of transmit and receive queues;
establishing a first linked list adapted to track memory blocks currently not used and available for use in a queue;
creating a plurality of queues, each said queue represented by a second linked list of one or more memory blocks of said queue memory, wherein a queue is created by allocating an available memory block from said queue memory removing said allocated memory block from said first linked list and creating said second linked list for representing the one or more memory blocks that make up said queue;
writing to a queue utilizing a write pointer for identifying the next location in a queue available for writing;
reading from a queue utilizing a read pointer for identifying the next location in a queue to be read;
increasing the size of a queue when a queue is full by allocating an additional memory block from said queue memory removing the allocated memory block from the first linked list and adding the newly allocated memory block to the second linked list; and
reducing the size of a queue when a memory block becomes empty by de-allocating, empty memory block, adding the de-allocated memory block to the first linked list and removing the de-allocated memory block from the second linked list. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification
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Current AssigneeHewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company), Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
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Original Assignee3Com Corporation (HP Inc.)
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InventorsBronstein, Zvika, Elran, Roni, Schzukin, Golan, Shimony, Ilan
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Primary Examiner(s)Gaffin, Jeffrey
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Assistant Examiner(s)CHEN, ALAN S
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Application NumberUS09/584,582Time in Patent Office1,357 DaysField of Search710/54, 710/56, 710/52, 710/53, 710/55US Class Current710/52CPC Class CodesH04L 12/5601 Transfer mode dependent, e....H04L 2012/5665 Interaction of ATM with oth...H04L 2012/5681 Buffer or queue managementH04L 47/50 Queue schedulingH04L 49/108 using shared central bufferH04L 49/90 Buffering arrangementsH04L 49/901 using storage descriptor, e...H04L 49/9036 Common buffer combined with...H04L 49/9078 using an external memory or...
